7  * V0.0X01.0X00 first version.
34 #define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x00)
45 #define THCV244_REG_CTRL_MODE		0x1600
46 #define THCV244_MODE_SW_STANDBY		0x0
47 #define THCV244_MODE_STREAMING		0x1a
49 #define THCV244_ADDR			0x0b
50 #define THCV241_ADDR			0x34
52 #define REG_NULL			0xFFFF
130 	{0x0b, 0x0050, 0x34, 0x00},
131 	{0x0b, 0x0070, 0x34, 0x00},
132 	{0x0b, 0x0090, 0x34, 0x00},
133 	{0x0b, 0x00B0, 0x34, 0x00},
134 	{0x0b, 0x0004, 0x03, 0x00},
135 	{0x0b, 0x0010, 0xF0, 0x00},
136 	{0x0b, 0x1704, 0x0F, 0x00},
137 	{0x0b, 0x0102, 0xAA, 0x00},
138 	{0x0b, 0x0103, 0xAA, 0x00},
139 	{0x0b, 0x0104, 0x00, 0x00},
140 	{0x0b, 0x0105, 0x00, 0x00},
141 	{0x0b, 0x0100, 0x03, 0x00},
142 	{0x0b, 0x010F, 0x25, 0x00},
143 	{0x0b, 0x010A, 0x15, 0x00},
144 	{0x0b, 0x0031, 0x02, 0x00},
145 	{0x0b, 0x0032, 0x10, 0x00},
146 	{0x0b, REG_NULL, 0x00, 0x00},
150 	{0x0b, 0x0010, 0xFF, 0x00},
151 	{0x0b, 0x1010, 0xA1, 0x00},
152 	{0x0b, 0x1011, 0x06, 0x00},
153 	{0x0b, 0x1014, 0xA1, 0x00},
154 	{0x0b, 0x1015, 0x06, 0x00},
155 	{0x0b, 0x1018, 0xA1, 0x00},
156 	{0x0b, 0x1019, 0x06, 0x00},
157 	{0x0b, 0x101C, 0xA1, 0x00},
158 	{0x0b, 0x101D, 0x06, 0x00},
159 	{0x0b, 0x1012, 0x00, 0x00},
160 	{0x0b, 0x1013, 0x01, 0x00},
161 	{0x0b, 0x1021, 0x28, 0x00},
162 	{0x0b, 0x1022, 0x02, 0x00},
163 	{0x0b, 0x1023, 0x11, 0x00},
164 	{0x0b, 0x1024, 0x00, 0x00},
165 	{0x0b, 0x1025, 0x00, 0x00},
166 	{0x0b, 0x1026, 0x00, 0x00},
167 	{0x0b, 0x1027, 0x07, 0x00},
168 	{0x0b, 0x1028, 0x00, 0x00},
169 	{0x0b, 0x1030, 0x18, 0x00},
170 	{0x0b, 0x1100, 0x01, 0x00},
171 	{0x0b, 0x1101, 0x01, 0x00},
172 	{0x0b, 0x1102, 0x01, 0x00},
173 	{0x0b, 0x1108, 0x01, 0x00},
174 	{0x0b, 0x1200, 0x01, 0x00},
175 	{0x0b, 0x1201, 0x01, 0x00},
176 	{0x0b, 0x1202, 0x01, 0x00},
177 	{0x0b, 0x1208, 0x01, 0x00},
178 	{0x0b, 0x1300, 0x01, 0x00},
179 	{0x0b, 0x1301, 0x01, 0x00},
180 	{0x0b, 0x1302, 0x01, 0x00},
181 	{0x0b, 0x1308, 0x01, 0x00},
182 	{0x0b, 0x1400, 0x01, 0x00},
183 	{0x0b, 0x1401, 0x01, 0x00},
184 	{0x0b, 0x1402, 0x01, 0x00},
185 	{0x0b, 0x1408, 0x01, 0x00},
186 	{0x0b, 0x1500, 0x01, 0x00},
187 	{0x0b, 0x1501, 0x0B, 0x00},
188 	{0x0b, 0x1502, 0x64, 0x00},
189 	{0x0b, 0x1504, 0x64, 0x00},
190 	{0x0b, 0x1506, 0x64, 0x00},
191 	{0x0b, 0x1508, 0x64, 0x00},
192 	{0x0b, 0x150B, 0xE4, 0x00},
193 	{0x0b, 0x150C, 0xE5, 0x00},
194 	{0x0b, 0x150D, 0xE6, 0x00},
195 	{0x0b, 0x150E, 0xE7, 0x00},
196 	// {0x0b, 0x1600, 0x1A, 0x00},
197 	{0x0b, 0x1601, 0x3B, 0x00},
198 	{0x0b, 0x1605, 0x2B, 0x00},
199 	{0x0b, 0x1606, 0x44, 0x00},
200 	{0x0b, 0x1609, 0x0E, 0x00},
201 	{0x0b, 0x160A, 0x17, 0x00},
202 	{0x0b, 0x160B, 0x0C, 0x00},
203 	{0x0b, 0x160D, 0x10, 0x00},
204 	{0x0b, 0x160E, 0x06, 0x00},
205 	{0x0b, 0x160F, 0x09, 0x00},
206 	{0x0b, 0x1610, 0x05, 0x00},
207 	{0x0b, 0x1611, 0x19, 0x00},
208 	{0x0b, 0x1612, 0x0D, 0x00},
209 	{0x0b, 0x1703, 0x01, 0x00},
210 	{0x0b, 0x1704, 0xFF, 0x00},
211 	{0x0b, 0x0032, 0x00, 0x00},
212 	{0x0b, 0x1003, 0x00, 0x00},
213 	{0x0b, 0x1004, 0x00, 0x00},
214 	{0x0b, 0x001B, 0x18, 0x00},
215 	{0x0b, 0x0032, 0x10, 0x00},
216 	{0x0b, 0x1005, 0x22, 0x00},
217 	{0x0b, 0x100C, 0x30, 0x00},
218 	{0x0b, 0x100D, 0x34, 0x00},
219 	{0x0b, REG_NULL, 0x00, 0x00},
223 	{0x34, 0xF3, 0x00, 0x00},
224 	{0x34, 0xF2, 0x22, 0x00},
225 	{0x34, 0xF0, 0x03, 0x00},
226 	{0x34, 0xFF, 0x19, 0x00},
227 	{0x34, 0xF6, 0x15, 0x00},
228 	{0x34, 0xC9, 0x05, 0x00},
229 	{0x34, 0xCA, 0x05, 0x00},
230 	{0x34, 0xFE, 0x21, 0x00},
231 	{0x34, 0x76, 0x10, 0x00},
232 	{0x34, 0x0F, 0x01, 0x00},
233 	{0x34, 0x11, 0x2C, 0x00},
234 	{0x34, 0x12, 0x00, 0x00},
235 	{0x34, 0x13, 0x00, 0x00},
236 	{0x34, 0x14, 0x00, 0x00},
237 	{0x34, 0x15, 0x44, 0x00},
238 	{0x34, 0x16, 0x01, 0x00},
239 	{0x34, 0x00, 0x00, 0x00},
240 	{0x34, 0x01, 0x00, 0x00},
241 	{0x34, 0x02, 0x00, 0x00},
242 	{0x34, 0x55, 0x00, 0x00},
243 	{0x34, 0x04, 0x00, 0x00},
244 	{0x34, 0x2B, 0x05, 0x00},
245 	{0x34, 0x2F, 0x00, 0x00},
246 	{0x34, 0x2D, 0x13, 0x00},
247 	{0x34, 0x2C, 0x01, 0x00},
248 	{0x34, 0x05, 0x01, 0x00},
249 	{0x34, 0x06, 0x01, 0x00},
250 	{0x34, 0x27, 0x00, 0x00},
251 	{0x34, 0x1D, 0x00, 0x00},
252 	{0x34, 0x1E, 0x00, 0x00},
253 	{0x34, 0x3D, 0x00, 0x00},
254 	{0x34, 0x3E, 0x0c, 0x00},
255 	{0x34, 0x3F, 0x02, 0x00},
256 	{0x34, REG_NULL, 0x00, 0x00},
260 	{0x0b, 0x1702, 0x01, 0x00},
261 	{0x0b, 0x1600, 0x00, 0x00},
262 	{0x0b, 0x1703, 0x00, 0x00},
263 	{0x0b, 0x1704, 0x00, 0x00},
264 	{0x0b, 0x1701, 0xFD, 0x00},
265 	{0x0b, 0x0001, 0x01, 0x50},
266 	{0x0b, 0x0050, 0x34, 0x00},
267 	{0x0b, 0x0070, 0x34, 0x00},
268 	{0x0b, 0x0090, 0x34, 0x00},
269 	{0x0b, 0x00B0, 0x34, 0x00},
270 	{0x0b, 0x0004, 0x03, 0x00},
271 	{0x0b, 0x0010, 0xF0, 0x00},
272 	{0x0b, 0x1704, 0x0F, 0x00},
273 	{0x0b, 0x0102, 0xAA, 0x00},
274 	{0x0b, 0x0103, 0xAA, 0x00},
275 	{0x0b, 0x0104, 0x00, 0x00},
276 	{0x0b, 0x0105, 0x00, 0x00},
277 	{0x0b, 0x0100, 0x03, 0x00},
278 	{0x0b, 0x010F, 0x25, 0x00},
279 	{0x0b, 0x010A, 0x15, 0x00},
280 	{0x0b, 0x0031, 0x02, 0x00},
281 	{0x0b, 0x0032, 0x00, 0x00},
282 	{0x0b, REG_NULL, 0x00, 0x00},
286 	{0x34, 0xFE, 0x21, 0x00},
287 	{0x34, 0x06, 0x00, 0x00},
288 	{0x34, 0x05, 0x00, 0x00},
289 	{0x34, 0x21, 0x00, 0x00},
290 	{0x34, 0x22, 0x00, 0x00},
291 	{0x34, 0x23, 0x00, 0x00},
292 	{0x34, 0xFF, 0xAA, 0x00},
293 	{0x0b, REG_NULL, 0x00, 0x00},
297 	{0x34, 0xF3, 0x00, 0x00},
298 	{0x34, 0xF2, 0x22, 0x00},
299 	{0x34, 0xF0, 0x03, 0x00},
300 	{0x34, 0xFF, 0x19, 0x00},
301 	{0x34, 0xF6, 0x15, 0x00},
302 	{0x34, 0xFE, 0x21, 0x00},
303 	{0x34, 0x2D, 0x03, 0x00},
304 	{0x34, 0x2C, 0x00, 0x00},
305 	{0x34, 0x21, 0x01, 0x00},
306 	{0x34, 0x22, 0x01, 0x00},
307 	{0x34, 0x23, 0x01, 0x00},
308 	{0x34, 0xFE, 0x00, 0x00},
309 	{0x0b, REG_NULL, 0x00, 0x00},
320 		.link_freq_idx = 0,
340 		buf[0] = reg >> 8;  in thine_write_reg()
341 		buf[1] = reg & 0xff;  in thine_write_reg()
343 		buf[0] = reg & 0xff;  in thine_write_reg()
360 			"%s, i2c_master_send err, client->addr = 0x%x, reg = 0x%x, val = 0x%x\n",  in thine_write_reg()
366 		"%s, i2c_master_send ok, client->addr = 0x%x, reg = 0x%x, val = 0x%x\n",  in thine_write_reg()
369 	return 0;  in thine_write_reg()
376 	int ret = 0;  in thcv244_write_array()
378 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {  in thcv244_write_array()
392 	int ret = 0;  in thcv241_write_array()
394 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {  in thcv241_write_array()
410 	__be32 data_be = 0;  in thcv244_read_reg()
419 	msgs[0].addr = client->addr;  in thcv244_read_reg()
420 	msgs[0].flags = 0;  in thcv244_read_reg()
421 	msgs[0].len = 2;  in thcv244_read_reg()
422 	msgs[0].buf = (u8 *)&reg_addr_be;  in thcv244_read_reg()
436 	return 0;  in thcv244_read_reg()
451 	int cur_best_fit = 0;  in thcv244_find_best_fit()
455 	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {  in thcv244_find_best_fit()
496 	return 0;  in thcv244_set_fmt()
522 	return 0;  in thcv244_get_fmt()
529 	if (code->index != 0)  in thcv244_enum_mbus_code()
533 	return 0;  in thcv244_enum_mbus_code()
551 	return 0;  in thcv244_enum_frame_sizes()
564 	return 0;  in thcv244_g_frame_interval()
570 	memset(inf, 0, sizeof(*inf));  in thcv244_get_module_inf()
599 	long ret = 0;  in thcv244_ioctl()
600 	u32 stream = 0;  in thcv244_ioctl()
645 	long ret = 0;  in thcv244_compat_ioctl32()
646 	u32 stream = 0;  in thcv244_compat_ioctl32()
729 	ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0x00fe,  in thcv244_thcv241_init()
730 					2, THCV244_REG_VALUE_08BIT, 0x11);  in thcv244_thcv241_init()
731 	ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x0032,  in thcv244_thcv241_init()
732 					2, THCV244_REG_VALUE_08BIT, 0x00);  in thcv244_thcv241_init()
735 	ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x0032,  in thcv244_thcv241_init()
736 					2, THCV244_REG_VALUE_08BIT, 0x00);  in thcv244_thcv241_init()
737 	ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0xfe,  in thcv244_thcv241_init()
738 					1, THCV244_REG_VALUE_08BIT, 0x21);  in thcv244_thcv241_init()
739 	ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0x3e,  in thcv244_thcv241_init()
740 					1, THCV244_REG_VALUE_08BIT, 0x0c);  in thcv244_thcv241_init()
742 	ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0x3e,  in thcv244_thcv241_init()
743 					1, THCV244_REG_VALUE_08BIT, 0x3c);  in thcv244_thcv241_init()
745 	ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x1600,  in thcv244_thcv241_init()
746 					2, THCV244_REG_VALUE_08BIT, 0x00);  in thcv244_thcv241_init()
761 	ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x0032,  in thcv244_thcv241_reset_initial()
762 					2, THCV244_REG_VALUE_08BIT, 0x10);  in thcv244_thcv241_reset_initial()
763 	ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0x00fe,  in thcv244_thcv241_reset_initial()
764 					1, THCV244_REG_VALUE_08BIT, 0x11);  in thcv244_thcv241_reset_initial()
765 	ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x0032,  in thcv244_thcv241_reset_initial()
766 					2, THCV244_REG_VALUE_08BIT, 0x00);  in thcv244_thcv241_reset_initial()
810 	int ret = 0;  in thcv244_s_stream()
825 		if (ret < 0) {  in thcv244_s_stream()
853 	int ret = 0;  in thcv244_s_power()
863 		if (ret < 0) {  in thcv244_s_power()
900 		if (ret < 0)  in __thcv244_power_on()
905 		gpiod_set_value_cansleep(thcv244->reset_gpio, 0);  in __thcv244_power_on()
908 	if (ret < 0) {  in __thcv244_power_on()
924 	return 0;  in __thcv244_power_on()
938 		gpiod_set_value_cansleep(thcv244->pwdn_gpio, 0);  in __thcv244_power_off()
941 		gpiod_set_value_cansleep(thcv244->reset_gpio, 0);  in __thcv244_power_off()
946 		if (ret < 0)  in __thcv244_power_off()
950 		gpiod_set_value_cansleep(thcv244->power_gpio, 0);  in __thcv244_power_off()
972 	return 0;  in thcv244_runtime_suspend()
980 				v4l2_subdev_get_try_format(sd, fh->pad, 0);  in thcv244_open()
981 	const struct thcv244_mode *def_mode = &supported_modes[0];  in thcv244_open()
993 	return 0;  in thcv244_open()
1010 	return 0;  in thcv244_enum_frame_interval()
1024 	return 0;  in thcv244_g_mbus_config()
1034 		sel->r.left = 0;  in thcv244_get_selection()
1036 		sel->r.top = 0;  in thcv244_get_selection()
1038 		return 0;  in thcv244_get_selection()
1099 			1, 0, link_freq_items);  in thcv244_initialize_controls()
1103 			0, THCV244_PIXEL_RATE,  in thcv244_initialize_controls()
1118 	return 0;  in thcv244_initialize_controls()
1129 	return 0;  in thcv244_check_sensor_id()
1136 	for (i = 0; i < THCV244_NUM_SUPPLIES; i++)  in thcv244_configure_regulators()
1157 		(DRIVER_VERSION & 0xff00) >> 8,  in thcv244_probe()
1158 		DRIVER_VERSION & 0x00ff);  in thcv244_probe()
1190 	thcv244->cur_mode = &supported_modes[0];  in thcv244_probe()
1249 	if (ret < 0)  in thcv244_probe()
1253 	memset(facing, 0, sizeof(facing));  in thcv244_probe()
1254 	if (strcmp(thcv244->module_facing, "back") == 0)  in thcv244_probe()
1255 		facing[0] = 'b';  in thcv244_probe()
1257 		facing[0] = 'f';  in thcv244_probe()
1272 	return 0;  in thcv244_probe()
1305 	return 0;  in thcv244_remove()
1317 	{ "thine,thcv244", 0 },