248 static int mipid02_write_reg(struct mipid02_dev *bridge, u16 reg, u8 val)  in mipid02_write_reg()  function
526 	ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1, 0);  in mipid02_stream_disable()
529 	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1, 0);  in mipid02_stream_disable()
532 	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1, 0);  in mipid02_stream_disable()
563 	ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1,  in mipid02_stream_enable()
567 	ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI);  in mipid02_stream_enable()
570 	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1,  in mipid02_stream_enable()
574 	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG2,  in mipid02_stream_enable()
578 	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1,  in mipid02_stream_enable()
582 	ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG2,  in mipid02_stream_enable()
586 	ret = mipid02_write_reg(bridge, MIPID02_MODE_REG1,  in mipid02_stream_enable()
590 	ret = mipid02_write_reg(bridge, MIPID02_MODE_REG2,  in mipid02_stream_enable()
594 	ret = mipid02_write_reg(bridge, MIPID02_DATA_ID_RREG,  in mipid02_stream_enable()
598 	ret = mipid02_write_reg(bridge, MIPID02_DATA_SELECTION_CTRL,  in mipid02_stream_enable()
602 	ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL,  in mipid02_stream_enable()
606 	ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL_EMB,  in mipid02_stream_enable()