68 	struct clk		*xvclk;  member
108 	ret = clk_prepare_enable(pisp_dmy->xvclk);  in __pisp_dmy_power_on()
110 		dev_err(dev, "Failed to enable xvclk\n");  in __pisp_dmy_power_on()
167 	clk_disable_unprepare(pisp_dmy->xvclk);  in __pisp_dmy_power_on()
185 	clk_disable_unprepare(pisp_dmy->xvclk);  in __pisp_dmy_power_off()
367 	pisp_dmy->xvclk = devm_clk_get(dev, "xvclk");  in pisp_dmy_analyze_dts()
368 	if (IS_ERR(pisp_dmy->xvclk)) {  in pisp_dmy_analyze_dts()
369 		dev_err(dev, "Failed to get xvclk\n");  in pisp_dmy_analyze_dts()
372 	ret = clk_set_rate(pisp_dmy->xvclk, PISP_DMY_XVCLK_FREQ);  in pisp_dmy_analyze_dts()
374 		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");  in pisp_dmy_analyze_dts()
377 	if (clk_get_rate(pisp_dmy->xvclk) != PISP_DMY_XVCLK_FREQ)  in pisp_dmy_analyze_dts()
378 		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");  in pisp_dmy_analyze_dts()