Lines Matching +full:0 +full:x4001
6 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
7 * V0.0X01.0X03 add enum_frame_interval function.
8 * V0.0X01.0X04 add quick stream on/off
9 * V0.0X01.0X05 add function g_mbus_config
10 * V0.0X01.0X06
43 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x06)
53 #define CHIP_ID 0x008858
54 #define OV8858_REG_CHIP_ID 0x300a
56 #define OV8858_REG_CTRL_MODE 0x0100
57 #define OV8858_MODE_SW_STANDBY 0x0
58 #define OV8858_MODE_STREAMING 0x1
60 #define OV8858_REG_EXPOSURE 0x3500
63 #define OV8858_VTS_MAX 0x7fff
65 #define OV8858_REG_GAIN_H 0x3508
66 #define OV8858_REG_GAIN_L 0x3509
67 #define OV8858_GAIN_H_MASK 0x07
69 #define OV8858_GAIN_L_MASK 0xff
70 #define OV8858_GAIN_MIN 0x80
71 #define OV8858_GAIN_MAX 0x7ff
73 #define OV8858_GAIN_DEFAULT 0x80
75 #define OV8858_REG_TEST_PATTERN 0x5e00
76 #define OV8858_TEST_PATTERN_ENABLE 0x80
77 #define OV8858_TEST_PATTERN_DISABLE 0x0
79 #define OV8858_REG_VTS 0x380e
81 #define REG_NULL 0xFFFF
90 #define OV8858_CHIP_REVISION_REG 0x302A
91 #define OV8858_R1A 0xb0
92 #define OV8858_R2A 0xb2
213 {0x01, "Sunny"},
214 {0x02, "Truly"},
215 {0x03, "A-kerr"},
216 {0x04, "LiteArray"},
217 {0x05, "Darling"},
218 {0x06, "Qtech"},
219 {0x07, "OFlim"},
220 {0x08, "Huaquan/Kingcom"},
221 {0x09, "Booyi"},
222 {0x0a, "Laimu"},
223 {0x0b, "WDSEN"},
224 {0x0c, "Sunrise"},
225 {0x0d, "CameraKing"},
226 {0x0e, "Sunniness/Riyong"},
227 {0x0f, "Tongju"},
228 {0x10, "Seasons/Sijichun"},
229 {0x11, "Foxconn"},
230 {0x12, "Importek"},
231 {0x13, "Altek"},
232 {0x14, "ABICO/Ability"},
233 {0x15, "Lite-on"},
234 {0x16, "Chicony"},
235 {0x17, "Primax"},
236 {0x18, "AVC"},
237 {0x19, "Suyin"},
238 {0x21, "Sharp"},
239 {0x31, "MCNEX"},
240 {0x32, "SEMCO"},
241 {0x33, "Partron"},
242 {0x41, "Reach/Zhongliancheng"},
243 {0x42, "BYD"},
244 {0x43, "OSTEC(AoShunChuang)"},
245 {0x44, "Chengli"},
246 {0x45, "Jiali"},
247 {0x46, "Chippack"},
248 {0x47, "RongSheng"},
249 {0x48, "ShineTech/ShenTai"},
250 {0x49, "Brodsands"},
251 {0x50, "Others"},
252 {0x51, "Method"},
253 {0x52, "Sunwin"},
254 {0x53, "LG"},
255 {0x54, "Goertek"},
256 {0x00, "Unknown"}
260 {0x10, "Largan 9565A1"},
261 {0x11, "Largan 9570A/A1"},
262 {0x12, "Largan 9569A2/A3"},
263 {0x13, "Largan 40108/A1"},
264 {0x14, "Largan 50030A1"},
265 {0x15, "Largan 40109A1"},
266 {0x16, "Largan 40100/A1"},
267 {0x17, "Largan 40112/A1"},
268 {0x30, "Sunny 3813A"},
269 {0x50, "Kantatsu R5AV08/BV"},
270 {0x51, "Kantatsu S5AE08"},
271 {0x52, "Kantatsu S5AE08"},
272 {0x78, "GSEO 8738"},
273 {0x79, "GSEO 8744"},
274 {0x7a, "GSEO 8742"},
275 {0x80, "Foxconn 8028"},
276 {0xd8, "XinXu DS-8335"},
277 {0xd9, "XinXu DS-8341"},
278 {0x00, "Unknown"}
286 //; Slave_ID=0x6c;
287 //{0x0103 ,0x01 }, software reset
288 {0x0100, 0x00},
289 {0x0100, 0x00},
290 {0x0100, 0x00},
291 {0x0100, 0x00},
292 {0x0302, 0x1e},
293 {0x0303, 0x00},
294 {0x0304, 0x03},
295 {0x030e, 0x00},
296 {0x030f, 0x09},
297 {0x0312, 0x01},
298 {0x031e, 0x0c},
299 {0x3600, 0x00},
300 {0x3601, 0x00},
301 {0x3602, 0x00},
302 {0x3603, 0x00},
303 {0x3604, 0x22},
304 {0x3605, 0x30},
305 {0x3606, 0x00},
306 {0x3607, 0x20},
307 {0x3608, 0x11},
308 {0x3609, 0x28},
309 {0x360a, 0x00},
310 {0x360b, 0x06},
311 {0x360c, 0xdc},
312 {0x360d, 0x40},
313 {0x360e, 0x0c},
314 {0x360f, 0x20},
315 {0x3610, 0x07},
316 {0x3611, 0x20},
317 {0x3612, 0x88},
318 {0x3613, 0x80},
319 {0x3614, 0x58},
320 {0x3615, 0x00},
321 {0x3616, 0x4a},
322 {0x3617, 0xb0},
323 {0x3618, 0x56},
324 {0x3619, 0x70},
325 {0x361a, 0x99},
326 {0x361b, 0x00},
327 {0x361c, 0x07},
328 {0x361d, 0x00},
329 {0x361e, 0x00},
330 {0x361f, 0x00},
331 {0x3638, 0xff},
332 {0x3633, 0x0c},
333 {0x3634, 0x0c},
334 {0x3635, 0x0c},
335 {0x3636, 0x0c},
336 {0x3645, 0x13},
337 {0x3646, 0x83},
338 {0x364a, 0x07},
339 {0x3015, 0x01},
340 {0x3018, 0x32},
341 {0x3020, 0x93},
342 {0x3022, 0x01},
343 {0x3031, 0x0a},
344 {0x3034, 0x00},
345 {0x3106, 0x01},
346 {0x3305, 0xf1},
347 {0x3308, 0x00},
348 {0x3309, 0x28},
349 {0x330a, 0x00},
350 {0x330b, 0x20},
351 {0x330c, 0x00},
352 {0x330d, 0x00},
353 {0x330e, 0x00},
354 {0x330f, 0x40},
355 {0x3307, 0x04},
356 {0x3500, 0x00},
357 {0x3501, 0x4d},
358 {0x3502, 0x40},
359 {0x3503, 0x00},
360 {0x3505, 0x80},
361 {0x3508, 0x04},
362 {0x3509, 0x00},
363 {0x350c, 0x00},
364 {0x350d, 0x80},
365 {0x3510, 0x00},
366 {0x3511, 0x02},
367 {0x3512, 0x00},
368 {0x3700, 0x18},
369 {0x3701, 0x0c},
370 {0x3702, 0x28},
371 {0x3703, 0x19},
372 {0x3704, 0x14},
373 {0x3705, 0x00},
374 {0x3706, 0x35},
375 {0x3707, 0x04},
376 {0x3708, 0x24},
377 {0x3709, 0x33},
378 {0x370a, 0x00},
379 {0x370b, 0xb5},
380 {0x370c, 0x04},
381 {0x3718, 0x12},
382 {0x3719, 0x31},
383 {0x3712, 0x42},
384 {0x3714, 0x24},
385 {0x371e, 0x19},
386 {0x371f, 0x40},
387 {0x3720, 0x05},
388 {0x3721, 0x05},
389 {0x3724, 0x06},
390 {0x3725, 0x01},
391 {0x3726, 0x06},
392 {0x3728, 0x05},
393 {0x3729, 0x02},
394 {0x372a, 0x03},
395 {0x372b, 0x53},
396 {0x372c, 0xa3},
397 {0x372d, 0x53},
398 {0x372e, 0x06},
399 {0x372f, 0x10},
400 {0x3730, 0x01},
401 {0x3731, 0x06},
402 {0x3732, 0x14},
403 {0x3733, 0x10},
404 {0x3734, 0x40},
405 {0x3736, 0x20},
406 {0x373a, 0x05},
407 {0x373b, 0x06},
408 {0x373c, 0x0a},
409 {0x373e, 0x03},
410 {0x3755, 0x10},
411 {0x3758, 0x00},
412 {0x3759, 0x4c},
413 {0x375a, 0x06},
414 {0x375b, 0x13},
415 {0x375c, 0x20},
416 {0x375d, 0x02},
417 {0x375e, 0x00},
418 {0x375f, 0x14},
419 {0x3768, 0x22},
420 {0x3769, 0x44},
421 {0x376a, 0x44},
422 {0x3761, 0x00},
423 {0x3762, 0x00},
424 {0x3763, 0x00},
425 {0x3766, 0xff},
426 {0x376b, 0x00},
427 {0x3772, 0x23},
428 {0x3773, 0x02},
429 {0x3774, 0x16},
430 {0x3775, 0x12},
431 {0x3776, 0x04},
432 {0x3777, 0x00},
433 {0x3778, 0x1b},
434 {0x37a0, 0x44},
435 {0x37a1, 0x3d},
436 {0x37a2, 0x3d},
437 {0x37a3, 0x00},
438 {0x37a4, 0x00},
439 {0x37a5, 0x00},
440 {0x37a6, 0x00},
441 {0x37a7, 0x44},
442 {0x37a8, 0x4c},
443 {0x37a9, 0x4c},
444 {0x3760, 0x00},
445 {0x376f, 0x01},
446 {0x37aa, 0x44},
447 {0x37ab, 0x2e},
448 {0x37ac, 0x2e},
449 {0x37ad, 0x33},
450 {0x37ae, 0x0d},
451 {0x37af, 0x0d},
452 {0x37b0, 0x00},
453 {0x37b1, 0x00},
454 {0x37b2, 0x00},
455 {0x37b3, 0x42},
456 {0x37b4, 0x42},
457 {0x37b5, 0x33},
458 {0x37b6, 0x00},
459 {0x37b7, 0x00},
460 {0x37b8, 0x00},
461 {0x37b9, 0xff},
462 {0x3800, 0x00},
463 {0x3801, 0x0c},
464 {0x3802, 0x00},
465 {0x3803, 0x0c},
466 {0x3804, 0x0c},
467 {0x3805, 0xd3},
468 {0x3806, 0x09},
469 {0x3807, 0xa3},
470 {0x3808, 0x06},
471 {0x3809, 0x60},
472 {0x380a, 0x04},
473 {0x380b, 0xc8},
474 {0x380c, 0x07},
475 {0x380d, 0x88},
476 {0x380e, 0x04},
477 {0x380f, 0xdc},
478 {0x3810, 0x00},
479 {0x3811, 0x04},
480 {0x3813, 0x02},
481 {0x3814, 0x03},
482 {0x3815, 0x01},
483 {0x3820, 0x00},
484 {0x3821, 0x67},
485 {0x382a, 0x03},
486 {0x382b, 0x01},
487 {0x3830, 0x08},
488 {0x3836, 0x02},
489 {0x3837, 0x18},
490 {0x3841, 0xff},
491 {0x3846, 0x48},
492 {0x3d85, 0x14},
493 {0x3f08, 0x08},
494 {0x3f0a, 0x80},
495 {0x4000, 0xf1},
496 {0x4001, 0x10},
497 {0x4005, 0x10},
498 {0x4002, 0x27},
499 {0x4009, 0x81},
500 {0x400b, 0x0c},
501 {0x401b, 0x00},
502 {0x401d, 0x00},
503 {0x4020, 0x00},
504 {0x4021, 0x04},
505 {0x4022, 0x04},
506 {0x4023, 0xb9},
507 {0x4024, 0x05},
508 {0x4025, 0x2a},
509 {0x4026, 0x05},
510 {0x4027, 0x2b},
511 {0x4028, 0x00},
512 {0x4029, 0x02},
513 {0x402a, 0x04},
514 {0x402b, 0x04},
515 {0x402c, 0x02},
516 {0x402d, 0x02},
517 {0x402e, 0x08},
518 {0x402f, 0x02},
519 {0x401f, 0x00},
520 {0x4034, 0x3f},
521 {0x403d, 0x04},
522 {0x4300, 0xff},
523 {0x4301, 0x00},
524 {0x4302, 0x0f},
525 {0x4316, 0x00},
526 {0x4500, 0x38},
527 {0x4503, 0x18},
528 {0x4600, 0x00},
529 {0x4601, 0xcb},
530 {0x481f, 0x32},
531 {0x4837, 0x16},
532 {0x4850, 0x10},
533 {0x4851, 0x32},
534 {0x4b00, 0x2a},
535 {0x4b0d, 0x00},
536 {0x4d00, 0x04},
537 {0x4d01, 0x18},
538 {0x4d02, 0xc3},
539 {0x4d03, 0xff},
540 {0x4d04, 0xff},
541 {0x4d05, 0xff},
542 {0x5000, 0x7e},
543 {0x5001, 0x01},
544 {0x5002, 0x08},
545 {0x5003, 0x20},
546 {0x5046, 0x12},
547 {0x5901, 0x00},
548 {0x5e00, 0x00},
549 {0x5e01, 0x41},
550 {0x382d, 0x7f},
551 {0x4825, 0x3a},
552 {0x4826, 0x40},
553 {0x4808, 0x25},
554 //{0x0100, 0x01},
555 {REG_NULL, 0x00},
564 {0x0100, 0x00},
565 {0x030e, 0x00}, // pll2_rdiv
566 {0x030f, 0x09}, // pll2_divsp
567 {0x0312, 0x01}, // pll2_pre_div0, pll2_r_divdac
568 {0x3015, 0x01}, //
569 {0x3501, 0x4d}, // exposure M
570 {0x3502, 0x40}, // exposure L
571 //{0x3508, 0x04}, // gain H
572 {0x3706, 0x35},
573 {0x370a, 0x00},
574 {0x370b, 0xb5},
575 {0x3778, 0x1b},
576 {0x3808, 0x06}, // x output size H
577 {0x3809, 0x60}, // x output size L
578 {0x380a, 0x04}, // y output size H
579 {0x380b, 0xc8}, // y output size L
580 {0x380c, 0x07}, // HTS H
581 {0x380d, 0x88}, // HTS L
582 {0x380e, 0x04}, // VTS H
583 {0x380f, 0xdc}, // VTS L
584 {0x3814, 0x03}, // x odd inc
585 {0x3821, 0x67}, // mirror on, bin on
586 {0x382a, 0x03}, // y odd inc
587 {0x3830, 0x08},
588 {0x3836, 0x02},
589 {0x3f0a, 0x80},
590 {0x4001, 0x10}, // total 128 black column
591 {0x4022, 0x04}, // Anchor left end H
592 {0x4023, 0xb9}, // Anchor left end L
593 {0x4024, 0x05}, // Anchor right start H
594 {0x4025, 0x2a}, // Anchor right start L
595 {0x4026, 0x05}, // Anchor right end H
596 {0x4027, 0x2b}, // Anchor right end L
597 {0x402b, 0x04}, // top black line number
598 {0x402e, 0x08}, // bottom black line start
599 {0x4500, 0x38},
600 {0x4600, 0x00},
601 {0x4601, 0xcb},
602 {0x382d, 0x7f},
604 {REG_NULL, 0x00},
613 {0x0100, 0x00},
615 {0x030e, 0x02}, // pll2_rdiv
616 {0x030f, 0x04}, // pll2_divsp
617 {0x0312, 0x03}, // pll2_pre_div0, pll2_r_divdac
618 {0x3015, 0x00},
619 {0x3501, 0x9a},
620 {0x3502, 0x20},
621 //{0x3508, 0x02},
622 {0x3706, 0x6a},
623 {0x370a, 0x01},
624 {0x370b, 0x6a},
625 {0x3778, 0x32},
626 {0x3808, 0x0c}, // x output size H
627 {0x3809, 0xc0}, // x output size L
628 {0x380a, 0x09}, // y output size H
629 {0x380b, 0x90}, // y output size L
630 {0x380c, 0x07}, // HTS H
631 {0x380d, 0x94}, // HTS L
632 {0x380e, 0x09}, // VTS H
633 {0x380f, 0xaa}, // VTS L
634 {0x3814, 0x01}, // x odd inc
635 {0x3821, 0x46}, // mirror on, bin off
636 {0x382a, 0x01}, // y odd inc
637 {0x3830, 0x06},
638 {0x3836, 0x01},
639 {0x3f0a, 0x00},
640 {0x4001, 0x00}, // total 256 black column
641 {0x4022, 0x0b}, // Anchor left end H
642 {0x4023, 0xc3}, // Anchor left end L
643 {0x4024, 0x0c}, // Anchor right start H
644 {0x4025, 0x36}, // Anchor right start L
645 {0x4026, 0x0c}, // Anchor right end H
646 {0x4027, 0x37}, // Anchor right end L
647 {0x402b, 0x08}, // top black line number
648 {0x402e, 0x0c}, // bottom black line start
649 {0x4500, 0x58},
650 {0x4600, 0x01},
651 {0x4601, 0x97},
652 {0x382d, 0xff},
654 {REG_NULL, 0x00},
662 {0x0103, 0x01}, //software reset
663 {0x0100, 0x00}, //software standby
664 {0x0100, 0x00}, //
665 {0x0100, 0x00}, //
666 {0x0100, 0x00}, //
667 {0x0302, 0x1e}, //pll1_multi
668 {0x0303, 0x00}, //pll1_divm
669 {0x0304, 0x03}, //pll1_div_mipi
670 {0x030e, 0x00}, //pll2_rdiv
671 {0x030f, 0x09}, //pll2_divsp
672 {0x0312, 0x01}, //pll2_pre_div0, pll2_r_divdac
673 {0x031e, 0x0c}, //pll1_no_lat
674 {0x3600, 0x00},
675 {0x3601, 0x00},
676 {0x3602, 0x00},
677 {0x3603, 0x00},
678 {0x3604, 0x22},
679 {0x3605, 0x30},
680 {0x3606, 0x00},
681 {0x3607, 0x20},
682 {0x3608, 0x11},
683 {0x3609, 0x28},
684 {0x360a, 0x00},
685 {0x360b, 0x06},
686 {0x360c, 0xdc},
687 {0x360d, 0x40},
688 {0x360e, 0x0c},
689 {0x360f, 0x20},
690 {0x3610, 0x07},
691 {0x3611, 0x20},
692 {0x3612, 0x88},
693 {0x3613, 0x80},
694 {0x3614, 0x58},
695 {0x3615, 0x00},
696 {0x3616, 0x4a},
697 {0x3617, 0xb0},
698 {0x3618, 0x56},
699 {0x3619, 0x70},
700 {0x361a, 0x99},
701 {0x361b, 0x00},
702 {0x361c, 0x07},
703 {0x361d, 0x00},
704 {0x361e, 0x00},
705 {0x361f, 0x00},
706 {0x3638, 0xff},
707 {0x3633, 0x0c},
708 {0x3634, 0x0c},
709 {0x3635, 0x0c},
710 {0x3636, 0x0c},
711 {0x3645, 0x13},
712 {0x3646, 0x83},
713 {0x364a, 0x07},
714 {0x3015, 0x01}, //
715 {0x3018, 0x72}, //MIPI 4 lane
716 {0x3020, 0x93}, //Clock switch output normal, pclk_div =/1
717 {0x3022, 0x01}, //pd_mipi enable when rst_sync
718 {0x3031, 0x0a}, //MIPI 10-bit mode
719 {0x3034, 0x00},
720 {0x3106, 0x01}, //sclk_div, sclk_pre_div
721 {0x3305, 0xf1},
722 {0x3308, 0x00},
723 {0x3309, 0x28},
724 {0x330a, 0x00},
725 {0x330b, 0x20},
726 {0x330c, 0x00},
727 {0x330d, 0x00},
728 {0x330e, 0x00},
729 {0x330f, 0x40},
730 {0x3307, 0x04},
731 {0x3500, 0x00}, //exposure H
732 {0x3501, 0x4d}, //exposure M
733 {0x3502, 0x40}, //exposure L
734 {0x3503, 0x00}, //gain delay 1 frame, exposure delay 1 frame, real gain
735 {0x3505, 0x80}, //gain option
736 {0x3508, 0x04}, //gain H
737 {0x3509, 0x00}, //gain L
738 {0x350c, 0x00}, //short gain H
739 {0x350d, 0x80}, //short gain L
740 {0x3510, 0x00}, //short exposure H
741 {0x3511, 0x02}, //short exposure M
742 {0x3512, 0x00}, //short exposure L
743 {0x3700, 0x18},
744 {0x3701, 0x0c},
745 {0x3702, 0x28},
746 {0x3703, 0x19},
747 {0x3704, 0x14},
748 {0x3705, 0x00},
749 {0x3706, 0x35},
750 {0x3707, 0x04},
751 {0x3708, 0x24},
752 {0x3709, 0x33},
753 {0x370a, 0x00},
754 {0x370b, 0xb5},
755 {0x370c, 0x04},
756 {0x3718, 0x12},
757 {0x3719, 0x31},
758 {0x3712, 0x42},
759 {0x3714, 0x24},
760 {0x371e, 0x19},
761 {0x371f, 0x40},
762 {0x3720, 0x05},
763 {0x3721, 0x05},
764 {0x3724, 0x06},
765 {0x3725, 0x01},
766 {0x3726, 0x06},
767 {0x3728, 0x05},
768 {0x3729, 0x02},
769 {0x372a, 0x03},
770 {0x372b, 0x53},
771 {0x372c, 0xa3},
772 {0x372d, 0x53},
773 {0x372e, 0x06},
774 {0x372f, 0x10},
775 {0x3730, 0x01},
776 {0x3731, 0x06},
777 {0x3732, 0x14},
778 {0x3733, 0x10},
779 {0x3734, 0x40},
780 {0x3736, 0x20},
781 {0x373a, 0x05},
782 {0x373b, 0x06},
783 {0x373c, 0x0a},
784 {0x373e, 0x03},
785 {0x3755, 0x10},
786 {0x3758, 0x00},
787 {0x3759, 0x4c},
788 {0x375a, 0x06},
789 {0x375b, 0x13},
790 {0x375c, 0x20},
791 {0x375d, 0x02},
792 {0x375e, 0x00},
793 {0x375f, 0x14},
794 {0x3768, 0x22},
795 {0x3769, 0x44},
796 {0x376a, 0x44},
797 {0x3761, 0x00},
798 {0x3762, 0x00},
799 {0x3763, 0x00},
800 {0x3766, 0xff},
801 {0x376b, 0x00},
802 {0x3772, 0x23},
803 {0x3773, 0x02},
804 {0x3774, 0x16},
805 {0x3775, 0x12},
806 {0x3776, 0x04},
807 {0x3777, 0x00},
808 {0x3778, 0x1b},
809 {0x37a0, 0x44},
810 {0x37a1, 0x3d},
811 {0x37a2, 0x3d},
812 {0x37a3, 0x00},
813 {0x37a4, 0x00},
814 {0x37a5, 0x00},
815 {0x37a6, 0x00},
816 {0x37a7, 0x44},
817 {0x37a8, 0x4c},
818 {0x37a9, 0x4c},
819 {0x3760, 0x00},
820 {0x376f, 0x01},
821 {0x37aa, 0x44},
822 {0x37ab, 0x2e},
823 {0x37ac, 0x2e},
824 {0x37ad, 0x33},
825 {0x37ae, 0x0d},
826 {0x37af, 0x0d},
827 {0x37b0, 0x00},
828 {0x37b1, 0x00},
829 {0x37b2, 0x00},
830 {0x37b3, 0x42},
831 {0x37b4, 0x42},
832 {0x37b5, 0x33},
833 {0x37b6, 0x00},
834 {0x37b7, 0x00},
835 {0x37b8, 0x00},
836 {0x37b9, 0xff},
837 {0x3800, 0x00}, //x start H
838 {0x3801, 0x0c}, //x start L
839 {0x3802, 0x00}, //y start H
840 {0x3803, 0x0c}, //y start L
841 {0x3804, 0x0c}, //x end H
842 {0x3805, 0xd3}, //x end L
843 {0x3806, 0x09}, //y end H
844 {0x3807, 0xa3}, //y end L
845 {0x3808, 0x06}, //x output size H
846 {0x3809, 0x60}, //x output size L
847 {0x380a, 0x04}, //y output size H
848 {0x380b, 0xc8}, //y output size L
849 {0x380c, 0x07}, //03}, //HTS H
850 {0x380d, 0x88}, //c4}, //HTS L
851 {0x380e, 0x04}, //VTS H
852 {0x380f, 0xdc}, //VTS L
853 {0x3810, 0x00}, //ISP x win H
854 {0x3811, 0x04}, //ISP x win L
855 {0x3813, 0x02}, //ISP y win L
856 {0x3814, 0x03}, //x odd inc
857 {0x3815, 0x01}, //x even inc
858 {0x3820, 0x00}, //vflip off
859 {0x3821, 0x67}, //mirror on, bin on
860 {0x382a, 0x03}, //y odd inc
861 {0x382b, 0x01}, //y even inc
862 {0x3830, 0x08},
863 {0x3836, 0x02},
864 {0x3837, 0x18},
865 {0x3841, 0xff}, //window auto size enable
866 {0x3846, 0x48},
867 {0x3d85, 0x14}, //OTP power up load data enable, setting disable
868 {0x3f08, 0x08},
869 {0x3f0a, 0x80},
870 {0x4000, 0xf1}, //out_range/format/gain/exp_chg_trig, median filter enable
871 {0x4001, 0x10}, //total 128 black column
872 {0x4005, 0x10}, //BLC target L
873 {0x4002, 0x27}, //value used to limit BLC offset
874 {0x4009, 0x81}, //final BLC offset limitation enable
875 {0x400b, 0x0c}, //DCBLC on, DCBLC manual mode on
876 {0x401b, 0x00}, //zero line R coefficient
877 {0x401d, 0x00}, //zoro line T coefficient
878 {0x4020, 0x00}, //Anchor left start H
879 {0x4021, 0x04}, //Anchor left start L
880 {0x4022, 0x04}, //Anchor left end H
881 {0x4023, 0xb9}, //Anchor left end L
882 {0x4024, 0x05}, //Anchor right start H
883 {0x4025, 0x2a}, //Anchor right start L
884 {0x4026, 0x05}, //Anchor right end H
885 {0x4027, 0x2b}, //Anchor right end L
886 {0x4028, 0x00}, //top zero line start
887 {0x4029, 0x02}, //top zero line number
888 {0x402a, 0x04}, //top black line start
889 {0x402b, 0x04}, //top black line number
890 {0x402c, 0x02}, //bottom zero line start
891 {0x402d, 0x02}, //bottom zoro line number
892 {0x402e, 0x08}, //bottom black line start
893 {0x402f, 0x02}, //bottom black line number
894 {0x401f, 0x00}, //interpolation x & y disable, Anchor one disable
895 {0x4034, 0x3f},
896 {0x403d, 0x04}, //md_precision_en
897 {0x4300, 0xff}, //clip max H
898 {0x4301, 0x00}, //clip min H
899 {0x4302, 0x0f}, //clip min L, clip max L
900 {0x4316, 0x00},
901 {0x4500, 0x38},
902 {0x4503, 0x18},
903 {0x4600, 0x00},
904 {0x4601, 0xcb},
905 {0x481f, 0x32}, //clk prepare min
906 {0x4837, 0x16}, //global timing
907 {0x4850, 0x10}, //lane 1 = 1, lane 0 = 0
908 {0x4851, 0x32}, //lane 3 = 3, lane 2 = 2
909 {0x4b00, 0x2a},
910 {0x4b0d, 0x00},
911 {0x4d00, 0x04}, //temperature sensor
912 {0x4d01, 0x18},
913 {0x4d02, 0xc3},
914 {0x4d03, 0xff},
915 {0x4d04, 0xff},
916 {0x4d05, 0xff}, //temperature sensor
917 {0x5000, 0x7e}, //slave/master AWB gain/statistics enable, BPC/WPC on
918 {0x5001, 0x01}, //BLC on
919 {0x5002, 0x08}, //H scale off, WBMATCH off, OTP_DPC off
920 {0x5003, 0x20}, //; DPC_DBC buffer control enable, WB
921 {0x5046, 0x12},
922 {0x5901, 0x00}, //H skip off, V skip off
923 {0x5e00, 0x00}, //test pattern off
924 {0x5e01, 0x41}, //window cut enable
925 {0x382d, 0x7f},
926 {0x4825, 0x3a}, //lpx_p_min
927 {0x4826, 0x40}, //hs_prepare_min
928 {0x4808, 0x25}, //wake up
929 {REG_NULL, 0x00},
938 {0x0100, 0x00},
939 {0x030f, 0x04}, //pll2_divsp
940 {0x3501, 0x9a}, //exposure M
941 {0x3502, 0x20}, //exposure L
942 //{0x3508, 0x02}, //gain H
943 {0x3700, 0x30},
944 {0x3701, 0x18},
945 {0x3702, 0x50},
946 {0x3703, 0x32},
947 {0x3704, 0x28},
948 {0x3706, 0x6a},
949 {0x3707, 0x08},
950 {0x3708, 0x48},
951 {0x3709, 0x66},
952 {0x370a, 0x01},
953 {0x370b, 0x6a},
954 {0x370c, 0x07},
955 {0x3718, 0x14},
956 {0x3712, 0x44},
957 {0x371e, 0x31},
958 {0x371f, 0x7f},
959 {0x3720, 0x0a},
960 {0x3721, 0x0a},
961 {0x3724, 0x0c},
962 {0x3725, 0x02},
963 {0x3726, 0x0c},
964 {0x3728, 0x0a},
965 {0x3729, 0x03},
966 {0x372a, 0x06},
967 {0x372b, 0xa6},
968 {0x372c, 0xa6},
969 {0x372d, 0xa6},
970 {0x372e, 0x0c},
971 {0x372f, 0x20},
972 {0x3730, 0x02},
973 {0x3731, 0x0c},
974 {0x3732, 0x28},
975 {0x3736, 0x30},
976 {0x373a, 0x0a},
977 {0x373b, 0x0b},
978 {0x373c, 0x14},
979 {0x373e, 0x06},
980 {0x375a, 0x0c},
981 {0x375b, 0x26},
982 {0x375d, 0x04},
983 {0x375f, 0x28},
984 {0x3772, 0x46},
985 {0x3773, 0x04},
986 {0x3774, 0x2c},
987 {0x3775, 0x13},
988 {0x3776, 0x08},
989 {0x3778, 0x16},
990 {0x37a0, 0x88},
991 {0x37a1, 0x7a},
992 {0x37a2, 0x7a},
993 {0x37a7, 0x88},
994 {0x37a8, 0x98},
995 {0x37a9, 0x98},
996 {0x37aa, 0x88},
997 {0x37ab, 0x5c},
998 {0x37ac, 0x5c},
999 {0x37ad, 0x55},
1000 {0x37ae, 0x19},
1001 {0x37af, 0x19},
1002 {0x37b3, 0x84},
1003 {0x37b4, 0x84},
1004 {0x37b5, 0x66},
1005 {0x3808, 0x0c}, //x output size H
1006 {0x3809, 0xc0}, //x output size L
1007 {0x380a, 0x09}, //y output size H
1008 {0x380b, 0x90}, //y output size L
1009 {0x380c, 0x07}, //HTS H
1010 {0x380d, 0x94}, //HTS L
1011 {0x380e, 0x09}, //VTS H
1012 {0x380f, 0xaa}, //VTS L
1013 {0x3814, 0x01}, //x odd inc
1014 {0x3821, 0x46}, //mirror on, bin off
1015 {0x382a, 0x01}, //y odd inc
1016 {0x3830, 0x06},
1017 {0x3836, 0x01},
1018 {0x3f08, 0x08},
1019 {0x3f0a, 0x00},
1020 {0x4001, 0x00}, //total 256 black column
1021 {0x4022, 0x0b}, //Anchor left end H
1022 {0x4023, 0xc3}, //Anchor left end L
1023 {0x4024, 0x0c}, //Anchor right start H
1024 {0x4025, 0x36}, //Anchor right start L
1025 {0x4026, 0x0c}, //Anchor right end H
1026 {0x4027, 0x37}, //Anchor right end L
1027 {0x402b, 0x08}, //top black line number
1028 {0x402e, 0x0c}, //bottom black line start
1029 {0x4500, 0x58},
1030 {0x4600, 0x01},
1031 {0x4601, 0x97},
1032 {0x382d, 0xff},
1033 {REG_NULL, 0x00},
1045 // AM19 : 3617 <- 0xC0
1047 // AM20 : change FWC_6K_EN to be default 0x3618=0x5a
1048 {0x0103, 0x01},// software reset for OVTATool only
1049 {0x0103, 0x01},// software reset
1050 {0x0100, 0x00},// software standby
1051 {0x0302, 0x1e},// pll1_multi
1052 {0x0303, 0x00},// pll1_divm
1053 {0x0304, 0x03},// pll1_div_mipi
1054 {0x030e, 0x02},// pll2_rdiv
1055 {0x030f, 0x04},// pll2_divsp
1056 {0x0312, 0x03},// pll2_pre_div0, pll2_r_divdac
1057 {0x031e, 0x0c},// pll1_no_lat
1058 {0x3600, 0x00},
1059 {0x3601, 0x00},
1060 {0x3602, 0x00},
1061 {0x3603, 0x00},
1062 {0x3604, 0x22},
1063 {0x3605, 0x20},
1064 {0x3606, 0x00},
1065 {0x3607, 0x20},
1066 {0x3608, 0x11},
1067 {0x3609, 0x28},
1068 {0x360a, 0x00},
1069 {0x360b, 0x05},
1070 {0x360c, 0xd4},
1071 {0x360d, 0x40},
1072 {0x360e, 0x0c},
1073 {0x360f, 0x20},
1074 {0x3610, 0x07},
1075 {0x3611, 0x20},
1076 {0x3612, 0x88},
1077 {0x3613, 0x80},
1078 {0x3614, 0x58},
1079 {0x3615, 0x00},
1080 {0x3616, 0x4a},
1081 {0x3617, 0x90},
1082 {0x3618, 0x5a},
1083 {0x3619, 0x70},
1084 {0x361a, 0x99},
1085 {0x361b, 0x0a},
1086 {0x361c, 0x07},
1087 {0x361d, 0x00},
1088 {0x361e, 0x00},
1089 {0x361f, 0x00},
1090 {0x3638, 0xff},
1091 {0x3633, 0x0f},
1092 {0x3634, 0x0f},
1093 {0x3635, 0x0f},
1094 {0x3636, 0x12},
1095 {0x3645, 0x13},
1096 {0x3646, 0x83},
1097 {0x364a, 0x07},
1098 {0x3015, 0x00},
1099 {0x3018, 0x32}, // MIPI 2 lane
1100 {0x3020, 0x93}, // Clock switch output normal, pclk_div =/1
1101 {0x3022, 0x01}, // pd_mipi enable when rst_sync
1102 {0x3031, 0x0a}, // MIPI 10-bit mode
1103 {0x3034, 0x00}, //
1104 {0x3106, 0x01}, // sclk_div, sclk_pre_div
1105 {0x3305, 0xf1},
1106 {0x3308, 0x00},
1107 {0x3309, 0x28},
1108 {0x330a, 0x00},
1109 {0x330b, 0x20},
1110 {0x330c, 0x00},
1111 {0x330d, 0x00},
1112 {0x330e, 0x00},
1113 {0x330f, 0x40},
1114 {0x3307, 0x04},
1115 {0x3500, 0x00}, // exposure H
1116 {0x3501, 0x4d}, // exposure M
1117 {0x3502, 0x40}, // exposure L
1118 {0x3503, 0x80}, // gain delay ?, exposure delay 1 frame, real gain
1119 {0x3505, 0x80}, // gain option
1120 {0x3508, 0x02}, // gain H
1121 {0x3509, 0x00}, // gain L
1122 {0x350c, 0x00}, // short gain H
1123 {0x350d, 0x80}, // short gain L
1124 {0x3510, 0x00}, // short exposure H
1125 {0x3511, 0x02}, // short exposure M
1126 {0x3512, 0x00}, // short exposure L
1127 {0x3700, 0x18},
1128 {0x3701, 0x0c},
1129 {0x3702, 0x28},
1130 {0x3703, 0x19},
1131 {0x3704, 0x14},
1132 {0x3705, 0x00},
1133 {0x3706, 0x82},
1134 {0x3707, 0x04},
1135 {0x3708, 0x24},
1136 {0x3709, 0x33},
1137 {0x370a, 0x01},
1138 {0x370b, 0x82},
1139 {0x370c, 0x04},
1140 {0x3718, 0x12},
1141 {0x3719, 0x31},
1142 {0x3712, 0x42},
1143 {0x3714, 0x24},
1144 {0x371e, 0x19},
1145 {0x371f, 0x40},
1146 {0x3720, 0x05},
1147 {0x3721, 0x05},
1148 {0x3724, 0x06},
1149 {0x3725, 0x01},
1150 {0x3726, 0x06},
1151 {0x3728, 0x05},
1152 {0x3729, 0x02},
1153 {0x372a, 0x03},
1154 {0x372b, 0x53},
1155 {0x372c, 0xa3},
1156 {0x372d, 0x53},
1157 {0x372e, 0x06},
1158 {0x372f, 0x10},
1159 {0x3730, 0x01},
1160 {0x3731, 0x06},
1161 {0x3732, 0x14},
1162 {0x3733, 0x10},
1163 {0x3734, 0x40},
1164 {0x3736, 0x20},
1165 {0x373a, 0x05},
1166 {0x373b, 0x06},
1167 {0x373c, 0x0a},
1168 {0x373e, 0x03},
1169 {0x3750, 0x0a},
1170 {0x3751, 0x0e},
1171 {0x3755, 0x10},
1172 {0x3758, 0x00},
1173 {0x3759, 0x4c},
1174 {0x375a, 0x06},
1175 {0x375b, 0x13},
1176 {0x375c, 0x20},
1177 {0x375d, 0x02},
1178 {0x375e, 0x00},
1179 {0x375f, 0x14},
1180 {0x3768, 0x22},
1181 {0x3769, 0x44},
1182 {0x376a, 0x44},
1183 {0x3761, 0x00},
1184 {0x3762, 0x00},
1185 {0x3763, 0x00},
1186 {0x3766, 0xff},
1187 {0x376b, 0x00},
1188 {0x3772, 0x23},
1189 {0x3773, 0x02},
1190 {0x3774, 0x16},
1191 {0x3775, 0x12},
1192 {0x3776, 0x04},
1193 {0x3777, 0x00},
1194 {0x3778, 0x17},
1195 {0x37a0, 0x44},
1196 {0x37a1, 0x3d},
1197 {0x37a2, 0x3d},
1198 {0x37a3, 0x00},
1199 {0x37a4, 0x00},
1200 {0x37a5, 0x00},
1201 {0x37a6, 0x00},
1202 {0x37a7, 0x44},
1203 {0x37a8, 0x4c},
1204 {0x37a9, 0x4c},
1205 {0x3760, 0x00},
1206 {0x376f, 0x01},
1207 {0x37aa, 0x44},
1208 {0x37ab, 0x2e},
1209 {0x37ac, 0x2e},
1210 {0x37ad, 0x33},
1211 {0x37ae, 0x0d},
1212 {0x37af, 0x0d},
1213 {0x37b0, 0x00},
1214 {0x37b1, 0x00},
1215 {0x37b2, 0x00},
1216 {0x37b3, 0x42},
1217 {0x37b4, 0x42},
1218 {0x37b5, 0x31},
1219 {0x37b6, 0x00},
1220 {0x37b7, 0x00},
1221 {0x37b8, 0x00},
1222 {0x37b9, 0xff},
1223 {0x3800, 0x00}, // x start H
1224 {0x3801, 0x0c}, // x start L
1225 {0x3802, 0x00}, // y start H
1226 {0x3803, 0x0c}, // y start L
1227 {0x3804, 0x0c}, // x end H
1228 {0x3805, 0xd3}, // x end L
1229 {0x3806, 0x09}, // y end H
1230 {0x3807, 0xa3}, // y end L
1231 {0x3808, 0x06}, // x output size H
1232 {0x3809, 0x60}, // x output size L
1233 {0x380a, 0x04}, // y output size H
1234 {0x380b, 0xc8}, // y output size L
1235 {0x380c, 0x07}, // HTS H
1236 {0x380d, 0x88}, // HTS L
1237 {0x380e, 0x04}, // VTS H
1238 {0x380f, 0xdc}, // VTS L
1239 {0x3810, 0x00}, // ISP x win H
1240 {0x3811, 0x04}, // ISP x win L
1241 {0x3813, 0x02}, // ISP y win L
1242 {0x3814, 0x03}, // x odd inc
1243 {0x3815, 0x01}, // x even inc
1244 {0x3820, 0x00}, // vflip off
1245 {0x3821, 0x67}, // mirror on, bin on
1246 {0x382a, 0x03}, // y odd inc
1247 {0x382b, 0x01}, // y even inc
1248 {0x3830, 0x08}, //
1249 {0x3836, 0x02}, //
1250 {0x3837, 0x18}, //
1251 {0x3841, 0xff}, // window auto size enable
1252 {0x3846, 0x48}, //
1253 {0x3d85, 0x16}, // OTP power up load data enable
1254 {0x3d8c, 0x73}, // OTP setting start High
1255 {0x3d8d, 0xde}, // OTP setting start Low
1256 {0x3f08, 0x08}, //
1257 {0x3f0a, 0x00}, //
1258 {0x4000, 0xf1}, // out_range_trig, format_chg_trig
1259 {0x4001, 0x10}, // total 128 black column
1260 {0x4005, 0x10}, // BLC target L
1261 {0x4002, 0x27}, // value used to limit BLC offset
1262 {0x4009, 0x81}, // final BLC offset limitation enable
1263 {0x400b, 0x0c}, // DCBLC on, DCBLC manual mode on
1264 {0x401b, 0x00}, // zero line R coefficient
1265 {0x401d, 0x00}, // zoro line T coefficient
1266 {0x4020, 0x00}, // Anchor left start H
1267 {0x4021, 0x04}, // Anchor left start L
1268 {0x4022, 0x06}, // Anchor left end H
1269 {0x4023, 0x00}, // Anchor left end L
1270 {0x4024, 0x0f}, // Anchor right start H
1271 {0x4025, 0x2a}, // Anchor right start L
1272 {0x4026, 0x0f}, // Anchor right end H
1273 {0x4027, 0x2b}, // Anchor right end L
1274 {0x4028, 0x00}, // top zero line start
1275 {0x4029, 0x02}, // top zero line number
1276 {0x402a, 0x04}, // top black line start
1277 {0x402b, 0x04}, // top black line number
1278 {0x402c, 0x00}, // bottom zero line start
1279 {0x402d, 0x02}, // bottom zoro line number
1280 {0x402e, 0x04}, // bottom black line start
1281 {0x402f, 0x04}, // bottom black line number
1282 {0x401f, 0x00}, // interpolation x/y disable, Anchor one disable
1283 {0x4034, 0x3f}, //
1284 {0x403d, 0x04}, // md_precision_en
1285 {0x4300, 0xff}, // clip max H
1286 {0x4301, 0x00}, // clip min H
1287 {0x4302, 0x0f}, // clip min L, clip max L
1288 {0x4316, 0x00}, //
1289 {0x4500, 0x58}, //
1290 {0x4503, 0x18}, //
1291 {0x4600, 0x00}, //
1292 {0x4601, 0xcb}, //
1293 {0x481f, 0x32}, // clk prepare min
1294 {0x4837, 0x16}, // global timing
1295 {0x4850, 0x10}, // lane 1 = 1, lane 0 = 0
1296 {0x4851, 0x32}, // lane 3 = 3, lane 2 = 2
1297 {0x4b00, 0x2a}, //
1298 {0x4b0d, 0x00}, //
1299 {0x4d00, 0x04}, // temperature sensor
1300 {0x4d01, 0x18}, //
1301 {0x4d02, 0xc3}, //
1302 {0x4d03, 0xff}, //
1303 {0x4d04, 0xff}, //
1304 {0x4d05, 0xff}, // temperature sensor
1305 {0x5000, 0xfe}, // lenc on, slave/master AWB gain/statistics enable
1306 {0x5001, 0x01}, // BLC on
1307 {0x5002, 0x08}, // H scale off, WBMATCH off, OTP_DPC
1308 {0x5003, 0x20}, // DPC_DBC buffer control enable, WB
1309 {0x5046, 0x12}, //
1310 {0x5780, 0x3e}, // DPC
1311 {0x5781, 0x0f}, //
1312 {0x5782, 0x44}, //
1313 {0x5783, 0x02}, //
1314 {0x5784, 0x01}, //
1315 {0x5785, 0x00}, //
1316 {0x5786, 0x00}, //
1317 {0x5787, 0x04}, //
1318 {0x5788, 0x02}, //
1319 {0x5789, 0x0f}, //
1320 {0x578a, 0xfd}, //
1321 {0x578b, 0xf5}, //
1322 {0x578c, 0xf5}, //
1323 {0x578d, 0x03}, //
1324 {0x578e, 0x08}, //
1325 {0x578f, 0x0c}, //
1326 {0x5790, 0x08}, //
1327 {0x5791, 0x04}, //
1328 {0x5792, 0x00}, //
1329 {0x5793, 0x52}, //
1330 {0x5794, 0xa3}, // DPC
1331 {0x5871, 0x0d}, // Lenc
1332 {0x5870, 0x18}, //
1333 {0x586e, 0x10}, //
1334 {0x586f, 0x08}, //
1335 {0x58f7, 0x01}, //
1336 {0x58f8, 0x3d}, // Lenc
1337 {0x5901, 0x00}, // H skip off, V skip off
1338 {0x5b00, 0x02}, // OTP DPC start address
1339 {0x5b01, 0x10}, // OTP DPC start address
1340 {0x5b02, 0x03}, // OTP DPC end address
1341 {0x5b03, 0xcf}, // OTP DPC end address
1342 {0x5b05, 0x6c}, // recover method = 2b11,
1343 {0x5e00, 0x00}, // use 0x3ff to test pattern off
1344 {0x5e01, 0x41}, // window cut enable
1345 {0x382d, 0x7f}, //
1346 {0x4825, 0x3a}, // lpx_p_min
1347 {0x4826, 0x40}, // hs_prepare_min
1348 {0x4808, 0x25}, // wake up delay in 1/1024 s
1349 {0x3763, 0x18}, //
1350 {0x3768, 0xcc}, //
1351 {0x470b, 0x28}, //
1352 {0x4202, 0x00}, //
1353 {0x400d, 0x10}, // BLC offset trigger L
1354 {0x4040, 0x04}, // BLC gain th2
1355 {0x403e, 0x04}, // BLC gain th1
1356 {0x4041, 0xc6}, // BLC
1357 {0x3007, 0x80},
1358 {0x400a, 0x01},
1359 {REG_NULL, 0x00},
1375 // AM19 : 3617 <- 0xC0
1377 // AM20 : change FWC_6K_EN to be default 0x3618=0x5a
1378 {0x0100, 0x00},
1379 {0x3501, 0x4d}, // exposure M
1380 {0x3502, 0x40}, // exposure L
1381 {0x3778, 0x17}, //
1382 {0x3808, 0x06}, // x output size H
1383 {0x3809, 0x60}, // x output size L
1384 {0x380a, 0x04}, // y output size H
1385 {0x380b, 0xc8}, // y output size L
1386 {0x380c, 0x07}, // HTS H
1387 {0x380d, 0x88}, // HTS L
1388 {0x380e, 0x04}, // VTS H
1389 {0x380f, 0xdc}, // VTS L
1390 {0x3814, 0x03}, // x odd inc
1391 {0x3821, 0x67}, // mirror on, bin on
1392 {0x382a, 0x03}, // y odd inc
1393 {0x3830, 0x08},
1394 {0x3836, 0x02},
1395 {0x3f0a, 0x00},
1396 {0x4001, 0x10}, // total 128 black column
1397 {0x4022, 0x06}, // Anchor left end H
1398 {0x4023, 0x00}, // Anchor left end L
1399 {0x4025, 0x2a}, // Anchor right start L
1400 {0x4027, 0x2b}, // Anchor right end L
1401 {0x402b, 0x04}, // top black line number
1402 {0x402f, 0x04}, // bottom black line number
1403 {0x4500, 0x58},
1404 {0x4600, 0x00},
1405 {0x4601, 0xcb},
1406 {0x382d, 0x7f},
1407 {0x0100, 0x01},
1408 {REG_NULL, 0x00},
1417 {0x0100, 0x00},
1418 {0x3501, 0x9a},// exposure M
1419 {0x3502, 0x20},// exposure L
1420 {0x3778, 0x1a},//
1421 {0x3808, 0x0c},// x output size H
1422 {0x3809, 0xc0},// x output size L
1423 {0x380a, 0x09},// y output size H
1424 {0x380b, 0x90},// y output size L
1425 {0x380c, 0x07},// HTS H
1426 {0x380d, 0x94},// HTS L
1427 {0x380e, 0x09},// VTS H
1428 {0x380f, 0xaa},// VTS L
1429 {0x3814, 0x01},// x odd inc
1430 {0x3821, 0x46},// mirror on, bin off
1431 {0x382a, 0x01},// y odd inc
1432 {0x3830, 0x06},
1433 {0x3836, 0x01},
1434 {0x3f0a, 0x00},
1435 {0x4001, 0x00},// total 256 black column
1436 {0x4022, 0x0c},// Anchor left end H
1437 {0x4023, 0x60},// Anchor left end L
1438 {0x4025, 0x36},// Anchor right start L
1439 {0x4027, 0x37},// Anchor right end L
1440 {0x402b, 0x08},// top black line number
1441 {0x402f, 0x08},// bottom black line number
1442 {0x4500, 0x58},
1443 {0x4600, 0x01},
1444 {0x4601, 0x97},
1445 {0x382d, 0xff},
1446 {REG_NULL, 0x00},
1458 // AM19 : 3617 <- 0xC0
1460 // AM20 : change FWC_6K_EN to be default 0x3618=0x5a
1461 {0x0103, 0x01}, // software reset for OVTATool only
1462 {0x0103, 0x01}, // software reset
1463 {0x0100, 0x00}, // software standby
1464 {0x0302, 0x1e}, // pll1_multi
1465 {0x0303, 0x00}, // pll1_divm
1466 {0x0304, 0x03}, // pll1_div_mipi
1467 {0x030e, 0x00}, // pll2_rdiv
1468 {0x030f, 0x04}, // pll2_divsp
1469 {0x0312, 0x01}, // pll2_pre_div0, pll2_r_divdac
1470 {0x031e, 0x0c}, // pll1_no_lat
1471 {0x3600, 0x00},
1472 {0x3601, 0x00},
1473 {0x3602, 0x00},
1474 {0x3603, 0x00},
1475 {0x3604, 0x22},
1476 {0x3605, 0x20},
1477 {0x3606, 0x00},
1478 {0x3607, 0x20},
1479 {0x3608, 0x11},
1480 {0x3609, 0x28},
1481 {0x360a, 0x00},
1482 {0x360b, 0x05},
1483 {0x360c, 0xd4},
1484 {0x360d, 0x40},
1485 {0x360e, 0x0c},
1486 {0x360f, 0x20},
1487 {0x3610, 0x07},
1488 {0x3611, 0x20},
1489 {0x3612, 0x88},
1490 {0x3613, 0x80},
1491 {0x3614, 0x58},
1492 {0x3615, 0x00},
1493 {0x3616, 0x4a},
1494 {0x3617, 0x90},
1495 {0x3618, 0x5a},
1496 {0x3619, 0x70},
1497 {0x361a, 0x99},
1498 {0x361b, 0x0a},
1499 {0x361c, 0x07},
1500 {0x361d, 0x00},
1501 {0x361e, 0x00},
1502 {0x361f, 0x00},
1503 {0x3638, 0xff},
1504 {0x3633, 0x0f},
1505 {0x3634, 0x0f},
1506 {0x3635, 0x0f},
1507 {0x3636, 0x12},
1508 {0x3645, 0x13},
1509 {0x3646, 0x83},
1510 {0x364a, 0x07},
1511 {0x3015, 0x01}, //
1512 {0x3018, 0x72}, // MIPI 4 lane
1513 {0x3020, 0x93}, // Clock switch output normal, pclk_div =/1
1514 {0x3022, 0x01}, // pd_mipi enable when rst_sync
1515 {0x3031, 0x0a}, // MIPI 10-bit mode
1516 {0x3034, 0x00}, //
1517 {0x3106, 0x01}, // sclk_div, sclk_pre_div
1518 {0x3305, 0xf1},
1519 {0x3308, 0x00},
1520 {0x3309, 0x28},
1521 {0x330a, 0x00},
1522 {0x330b, 0x20},
1523 {0x330c, 0x00},
1524 {0x330d, 0x00},
1525 {0x330e, 0x00},
1526 {0x330f, 0x40},
1527 {0x3307, 0x04},
1528 {0x3500, 0x00}, // exposure H
1529 {0x3501, 0x4d}, // exposure M
1530 {0x3502, 0x40}, // exposure L
1531 {0x3503, 0x80}, // gain delay ?, exposure delay 1 frame, real gain
1532 {0x3505, 0x80}, // gain option
1533 {0x3508, 0x04}, // gain H
1534 {0x3509, 0x00}, // gain L
1535 {0x350c, 0x00}, // short gain H
1536 {0x350d, 0x80}, // short gain L
1537 {0x3510, 0x00}, // short exposure H
1538 {0x3511, 0x02}, // short exposure M
1539 {0x3512, 0x00}, // short exposure L
1540 {0x3700, 0x30},
1541 {0x3701, 0x18},
1542 {0x3702, 0x50},
1543 {0x3703, 0x32},
1544 {0x3704, 0x28},
1545 {0x3705, 0x00},
1546 {0x3706, 0x82},
1547 {0x3707, 0x08},
1548 {0x3708, 0x48},
1549 {0x3709, 0x66},
1550 {0x370a, 0x01},
1551 {0x370b, 0x82},
1552 {0x370c, 0x07},
1553 {0x3718, 0x14},
1554 {0x3719, 0x31},
1555 {0x3712, 0x44},
1556 {0x3714, 0x24},
1557 {0x371e, 0x31},
1558 {0x371f, 0x7f},
1559 {0x3720, 0x0a},
1560 {0x3721, 0x0a},
1561 {0x3724, 0x0c},
1562 {0x3725, 0x02},
1563 {0x3726, 0x0c},
1564 {0x3728, 0x0a},
1565 {0x3729, 0x03},
1566 {0x372a, 0x06},
1567 {0x372b, 0xa6},
1568 {0x372c, 0xa6},
1569 {0x372d, 0xa6},
1570 {0x372e, 0x0c},
1571 {0x372f, 0x20},
1572 {0x3730, 0x02},
1573 {0x3731, 0x0c},
1574 {0x3732, 0x28},
1575 {0x3733, 0x10},
1576 {0x3734, 0x40},
1577 {0x3736, 0x30},
1578 {0x373a, 0x0a},
1579 {0x373b, 0x0b},
1580 {0x373c, 0x14},
1581 {0x373e, 0x06},
1582 {0x3750, 0x0a},
1583 {0x3751, 0x0e},
1584 {0x3755, 0x10},
1585 {0x3758, 0x00},
1586 {0x3759, 0x4c},
1587 {0x375a, 0x0c},
1588 {0x375b, 0x26},
1589 {0x375c, 0x20},
1590 {0x375d, 0x04},
1591 {0x375e, 0x00},
1592 {0x375f, 0x28},
1593 {0x3768, 0x22},
1594 {0x3769, 0x44},
1595 {0x376a, 0x44},
1596 {0x3761, 0x00},
1597 {0x3762, 0x00},
1598 {0x3763, 0x00},
1599 {0x3766, 0xff},
1600 {0x376b, 0x00},
1601 {0x3772, 0x46},
1602 {0x3773, 0x04},
1603 {0x3774, 0x2c},
1604 {0x3775, 0x13},
1605 {0x3776, 0x08},
1606 {0x3777, 0x00},
1607 {0x3778, 0x17},
1608 {0x37a0, 0x88},
1609 {0x37a1, 0x7a},
1610 {0x37a2, 0x7a},
1611 {0x37a3, 0x00},
1612 {0x37a4, 0x00},
1613 {0x37a5, 0x00},
1614 {0x37a6, 0x00},
1615 {0x37a7, 0x88},
1616 {0x37a8, 0x98},
1617 {0x37a9, 0x98},
1618 {0x3760, 0x00},
1619 {0x376f, 0x01},
1620 {0x37aa, 0x88},
1621 {0x37ab, 0x5c},
1622 {0x37ac, 0x5c},
1623 {0x37ad, 0x55},
1624 {0x37ae, 0x19},
1625 {0x37af, 0x19},
1626 {0x37b0, 0x00},
1627 {0x37b1, 0x00},
1628 {0x37b2, 0x00},
1629 {0x37b3, 0x84},
1630 {0x37b4, 0x84},
1631 {0x37b5, 0x60},
1632 {0x37b6, 0x00},
1633 {0x37b7, 0x00},
1634 {0x37b8, 0x00},
1635 {0x37b9, 0xff},
1636 {0x3800, 0x00}, // x start H
1637 {0x3801, 0x0c}, // x start L
1638 {0x3802, 0x00}, // y start H
1639 {0x3803, 0x0c}, // y start L
1640 {0x3804, 0x0c}, // x end H
1641 {0x3805, 0xd3}, // x end L
1642 {0x3806, 0x09}, // y end H
1643 {0x3807, 0xa3}, // y end L
1644 {0x3808, 0x06}, // x output size H
1645 {0x3809, 0x60}, // x output size L
1646 {0x380a, 0x04}, // y output size H
1647 {0x380b, 0xc8}, // y output size L
1648 {0x380c, 0x07}, // HTS H
1649 {0x380d, 0x88}, // HTS L
1650 {0x380e, 0x04}, // VTS H
1651 {0x380f, 0xdc}, // VTS L
1652 {0x3810, 0x00}, // ISP x win H
1653 {0x3811, 0x04}, // ISP x win L
1654 {0x3813, 0x02}, // ISP y win L
1655 {0x3814, 0x03}, // x odd inc
1656 {0x3815, 0x01}, // x even inc
1657 {0x3820, 0x00}, // vflip off
1658 {0x3821, 0x67}, // mirror on, bin o
1659 {0x382a, 0x03}, // y odd inc
1660 {0x382b, 0x01}, // y even inc
1661 {0x3830, 0x08},
1662 {0x3836, 0x02},
1663 {0x3837, 0x18},
1664 {0x3841, 0xff}, // window auto size enable
1665 {0x3846, 0x48}, //
1666 {0x3d85, 0x16}, // OTP power up load data/setting enable enable
1667 {0x3d8c, 0x73}, // OTP setting start High
1668 {0x3d8d, 0xde}, // OTP setting start Low
1669 {0x3f08, 0x10}, //
1670 {0x3f0a, 0x00}, //
1671 {0x4000, 0xf1}, // out_range/format_chg/gain/exp_chg trig enable
1672 {0x4001, 0x10}, // total 128 black column
1673 {0x4005, 0x10}, // BLC target L
1674 {0x4002, 0x27}, // value used to limit BLC offset
1675 {0x4009, 0x81}, // final BLC offset limitation enable
1676 {0x400b, 0x0c}, // DCBLC on, DCBLC manual mode on
1677 {0x401b, 0x00}, // zero line R coefficient
1678 {0x401d, 0x00}, // zoro line T coefficient
1679 {0x4020, 0x00}, // Anchor left start H
1680 {0x4021, 0x04}, // Anchor left start L
1681 {0x4022, 0x06}, // Anchor left end H
1682 {0x4023, 0x00}, // Anchor left end L
1683 {0x4024, 0x0f}, // Anchor right start H
1684 {0x4025, 0x2a}, // Anchor right start L
1685 {0x4026, 0x0f}, // Anchor right end H
1686 {0x4027, 0x2b}, // Anchor right end L
1687 {0x4028, 0x00}, // top zero line start
1688 {0x4029, 0x02}, // top zero line number
1689 {0x402a, 0x04}, // top black line start
1690 {0x402b, 0x04}, // top black line number
1691 {0x402c, 0x00}, // bottom zero line start
1692 {0x402d, 0x02}, // bottom zoro line number
1693 {0x402e, 0x04}, // bottom black line start
1694 {0x402f, 0x04}, // bottom black line number
1695 {0x401f, 0x00}, // interpolation x/y disable, Anchor one disable
1696 {0x4034, 0x3f},
1697 {0x403d, 0x04}, // md_precision_en
1698 {0x4300, 0xff}, // clip max H
1699 {0x4301, 0x00}, // clip min H
1700 {0x4302, 0x0f}, // clip min L, clip max L
1701 {0x4316, 0x00},
1702 {0x4500, 0x58},
1703 {0x4503, 0x18},
1704 {0x4600, 0x00},
1705 {0x4601, 0xcb},
1706 {0x481f, 0x32}, // clk prepare min
1707 {0x4837, 0x16}, // global timing
1708 {0x4850, 0x10}, // lane 1 = 1, lane 0 = 0
1709 {0x4851, 0x32}, // lane 3 = 3, lane 2 = 2
1710 {0x4b00, 0x2a},
1711 {0x4b0d, 0x00},
1712 {0x4d00, 0x04}, // temperature sensor
1713 {0x4d01, 0x18}, //
1714 {0x4d02, 0xc3}, //
1715 {0x4d03, 0xff}, //
1716 {0x4d04, 0xff}, //
1717 {0x4d05, 0xff}, // temperature sensor
1718 {0x5000, 0xfe}, // lenc on, slave/master AWB gain/statistics enable
1719 {0x5001, 0x01}, // BLC on
1720 {0x5002, 0x08}, // WBMATCH sensor's gain, H scale/WBMATCH/OTP_DPC off
1721 {0x5003, 0x20}, // DPC_DBC buffer control enable, WB
1722 {0x5046, 0x12}, //
1723 {0x5780, 0x3e}, // DPC
1724 {0x5781, 0x0f}, //
1725 {0x5782, 0x44}, //
1726 {0x5783, 0x02}, //
1727 {0x5784, 0x01}, //
1728 {0x5785, 0x00}, //
1729 {0x5786, 0x00}, //
1730 {0x5787, 0x04}, //
1731 {0x5788, 0x02}, //
1732 {0x5789, 0x0f}, //
1733 {0x578a, 0xfd}, //
1734 {0x578b, 0xf5}, //
1735 {0x578c, 0xf5}, //
1736 {0x578d, 0x03}, //
1737 {0x578e, 0x08}, //
1738 {0x578f, 0x0c}, //
1739 {0x5790, 0x08}, //
1740 {0x5791, 0x04}, //
1741 {0x5792, 0x00}, //
1742 {0x5793, 0x52}, //
1743 {0x5794, 0xa3}, // DPC
1744 {0x5871, 0x0d}, // Lenc
1745 {0x5870, 0x18}, //
1746 {0x586e, 0x10}, //
1747 {0x586f, 0x08}, //
1748 {0x58f7, 0x01}, //
1749 {0x58f8, 0x3d}, // Lenc
1750 {0x5901, 0x00}, // H skip off, V skip off
1751 {0x5b00, 0x02}, // OTP DPC start address
1752 {0x5b01, 0x10}, // OTP DPC start address
1753 {0x5b02, 0x03}, // OTP DPC end address
1754 {0x5b03, 0xcf}, // OTP DPC end address
1755 {0x5b05, 0x6c}, // recover method = 2b11
1756 {0x5e00, 0x00}, // use 0x3ff to test pattern off
1757 {0x5e01, 0x41}, // window cut enable
1758 {0x382d, 0x7f}, //
1759 {0x4825, 0x3a}, // lpx_p_min
1760 {0x4826, 0x40}, // hs_prepare_min
1761 {0x4808, 0x25}, // wake up delay in 1/1024 s
1762 {0x3763, 0x18},
1763 {0x3768, 0xcc},
1764 {0x470b, 0x28},
1765 {0x4202, 0x00},
1766 {0x400d, 0x10}, // BLC offset trigger L
1767 {0x4040, 0x04}, // BLC gain th2
1768 {0x403e, 0x04}, // BLC gain th1
1769 {0x4041, 0xc6}, // BLC
1770 {0x3007, 0x80},
1771 {0x400a, 0x01},
1772 {REG_NULL, 0x00},
1781 {0x0100, 0x00},
1782 {0x3501, 0x9a}, // exposure M
1783 {0x3502, 0x20}, // exposure L
1784 {0x3508, 0x02}, // gain H
1785 {0x3808, 0x0c}, // x output size H
1786 {0x3809, 0xc0}, // x output size L
1787 {0x380a, 0x09}, // y output size H
1788 {0x380b, 0x90}, // y output size L
1789 {0x380c, 0x07}, // HTS H
1790 {0x380d, 0x94}, // HTS L
1791 {0x380e, 0x0a}, // VTS H
1792 {0x380f, 0x00}, // VTS L
1793 {0x3814, 0x01}, // x odd inc
1794 {0x3821, 0x46}, // mirror on, bin off
1795 {0x382a, 0x01}, // y odd inc
1796 {0x3830, 0x06},
1797 {0x3836, 0x01},
1798 {0x3f0a, 0x00},
1799 {0x4001, 0x00}, // total 256 black column
1800 {0x4022, 0x0c}, // Anchor left end H
1801 {0x4023, 0x60}, // Anchor left end L
1802 {0x4025, 0x36}, // Anchor right start L
1803 {0x4027, 0x37}, // Anchor right end L
1804 {0x402b, 0x08}, // top black line number
1805 {0x402f, 0x08}, // interpolation x/y disable, Anchor one disable
1806 {0x4500, 0x58},
1807 {0x4600, 0x01},
1808 {0x4601, 0x97},
1809 {0x382d, 0xff},
1810 {0x030d, 0x1f},
1811 {REG_NULL, 0x00},
1822 .exp_def = 0x09a0,
1823 .hts_def = 0x0794 * 2,
1824 .vts_def = 0x09aa,
1834 .exp_def = 0x04d0,
1835 .hts_def = 0x0788,
1836 .vts_def = 0x04dc,
1849 .exp_def = 0x09a0,
1850 .hts_def = 0x0794 * 2,
1851 .vts_def = 0x09aa,
1864 .exp_def = 0x09a0,
1865 .hts_def = 0x0794 * 2,
1866 .vts_def = 0x09aa,
1876 .exp_def = 0x04d0,
1877 .hts_def = 0x0788,
1878 .vts_def = 0x04dc,
1891 .exp_def = 0x09a0,
1892 .hts_def = 0x0794 * 2,
1893 .vts_def = 0x0a00,
1924 buf[0] = reg >> 8; in ov8858_write_reg()
1925 buf[1] = reg & 0xff; in ov8858_write_reg()
1938 return 0; in ov8858_write_reg()
1945 int ret = 0; in ov8858_write_array()
1947 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) in ov8858_write_array()
1961 __be32 data_be = 0; in ov8858_read_reg()
1970 msgs[0].addr = client->addr; in ov8858_read_reg()
1971 msgs[0].flags = 0; in ov8858_read_reg()
1972 msgs[0].len = 2; in ov8858_read_reg()
1973 msgs[0].buf = (u8 *)®_addr_be; in ov8858_read_reg()
1987 return 0; in ov8858_read_reg()
2003 int cur_best_fit = 0; in ov8858_find_best_fit()
2007 for (i = 0; i < ov8858->cfg_num; i++) { in ov8858_find_best_fit()
2053 return 0; in ov8858_set_fmt()
2079 return 0; in ov8858_get_fmt()
2086 if (code->index != 0) in ov8858_enum_mbus_code()
2090 return 0; in ov8858_enum_mbus_code()
2110 return 0; in ov8858_enum_frame_sizes()
2136 return 0; in ov8858_g_frame_interval()
2146 if (otp_r1a->flag & 0x80) { in ov8858_get_r1a_otp()
2152 for (i = 0; i < ARRAY_SIZE(ov8858_module_info) - 1; i++) { in ov8858_get_r1a_otp()
2159 for (i = 0; i < ARRAY_SIZE(ov8858_lens_info) - 1; i++) { in ov8858_get_r1a_otp()
2168 if (otp_r1a->flag & 0x40) { in ov8858_get_r1a_otp()
2169 if (otp_r1a->light_rg == 0) in ov8858_get_r1a_otp()
2175 if (otp_r1a->light_bg == 0) in ov8858_get_r1a_otp()
2184 inf->awb.gr_value = 0x200; in ov8858_get_r1a_otp()
2185 inf->awb.gb_value = 0x200; in ov8858_get_r1a_otp()
2187 inf->awb.golden_r_value = 0; in ov8858_get_r1a_otp()
2188 inf->awb.golden_b_value = 0; in ov8858_get_r1a_otp()
2189 inf->awb.golden_gr_value = 0; in ov8858_get_r1a_otp()
2190 inf->awb.golden_gb_value = 0; in ov8858_get_r1a_otp()
2194 if (otp_r1a->flag & 0x20) { in ov8858_get_r1a_otp()
2197 inf->af.af_otp[0].vcm_start = otp_r1a->vcm_start; in ov8858_get_r1a_otp()
2198 inf->af.af_otp[0].vcm_end = otp_r1a->vcm_end; in ov8858_get_r1a_otp()
2199 inf->af.af_otp[0].vcm_dir = otp_r1a->vcm_dir; in ov8858_get_r1a_otp()
2203 if (otp_r1a->flag & 0x10) { in ov8858_get_r1a_otp()
2205 inf->lsc.decimal_bits = 0; in ov8858_get_r1a_otp()
2209 j = 0; in ov8858_get_r1a_otp()
2210 for (i = 0; i < 36; i++) { in ov8858_get_r1a_otp()
2214 for (i = 0; i < 36; i++) in ov8858_get_r1a_otp()
2216 for (i = 0; i < 36; i++) in ov8858_get_r1a_otp()
2228 if (otp_r2a->flag & 0xC0) { in ov8858_get_r2a_otp()
2234 for (i = 0; i < ARRAY_SIZE(ov8858_module_info) - 1; i++) { in ov8858_get_r2a_otp()
2241 for (i = 0; i < ARRAY_SIZE(ov8858_lens_info) - 1; i++) { in ov8858_get_r2a_otp()
2254 inf->awb.gr_value = 0x200; in ov8858_get_r2a_otp()
2255 inf->awb.gb_value = 0x200; in ov8858_get_r2a_otp()
2257 inf->awb.golden_r_value = 0; in ov8858_get_r2a_otp()
2258 inf->awb.golden_b_value = 0; in ov8858_get_r2a_otp()
2259 inf->awb.golden_gr_value = 0; in ov8858_get_r2a_otp()
2260 inf->awb.golden_gb_value = 0; in ov8858_get_r2a_otp()
2264 if (otp_r2a->flag & 0x20) { in ov8858_get_r2a_otp()
2267 inf->af.af_otp[0].vcm_start = otp_r2a->vcm_start; in ov8858_get_r2a_otp()
2268 inf->af.af_otp[0].vcm_end = otp_r2a->vcm_end; in ov8858_get_r2a_otp()
2269 inf->af.af_otp[0].vcm_dir = otp_r2a->vcm_dir; in ov8858_get_r2a_otp()
2273 if (otp_r2a->flag & 0x10) { in ov8858_get_r2a_otp()
2275 inf->lsc.decimal_bits = 0; in ov8858_get_r2a_otp()
2279 j = 0; in ov8858_get_r2a_otp()
2280 for (i = 0; i < 80; i++) { in ov8858_get_r2a_otp()
2284 for (i = 0; i < 80; i++) in ov8858_get_r2a_otp()
2286 for (i = 0; i < 80; i++) in ov8858_get_r2a_otp()
2329 long ret = 0; in ov8858_ioctl()
2330 u32 stream = 0; in ov8858_ioctl()
2373 long ret = 0; in ov8858_compat_ioctl32()
2374 u32 stream = 0; in ov8858_compat_ioctl32()
2435 u32 golden_bg_ratio = 0; in ov8858_apply_otp_r1a()
2436 u32 golden_rg_ratio = 0; in ov8858_apply_otp_r1a()
2437 u32 golden_g_value = 0; in ov8858_apply_otp_r1a()
2443 golden_bg_ratio = awb_cfg->golden_b_value * 0x200 / golden_g_value; in ov8858_apply_otp_r1a()
2444 golden_rg_ratio = awb_cfg->golden_r_value * 0x200 / golden_g_value; in ov8858_apply_otp_r1a()
2448 if ((otp_ptr->flag & 0x40) && golden_bg_ratio && golden_rg_ratio) { in ov8858_apply_otp_r1a()
2449 if (otp_ptr->light_rg == 0) in ov8858_apply_otp_r1a()
2459 if (otp_ptr->light_bg == 0) in ov8858_apply_otp_r1a()
2481 R_gain = 0x400 * R_gain / (base_gain); in ov8858_apply_otp_r1a()
2482 B_gain = 0x400 * B_gain / (base_gain); in ov8858_apply_otp_r1a()
2483 G_gain = 0x400 * G_gain / (base_gain); in ov8858_apply_otp_r1a()
2486 if (R_gain > 0x400) { in ov8858_apply_otp_r1a()
2487 ov8858_write_1byte(client, 0x5032, R_gain >> 8); in ov8858_apply_otp_r1a()
2488 ov8858_write_1byte(client, 0x5033, R_gain & 0x00ff); in ov8858_apply_otp_r1a()
2490 if (G_gain > 0x400) { in ov8858_apply_otp_r1a()
2491 ov8858_write_1byte(client, 0x5034, G_gain >> 8); in ov8858_apply_otp_r1a()
2492 ov8858_write_1byte(client, 0x5035, G_gain & 0x00ff); in ov8858_apply_otp_r1a()
2494 if (B_gain > 0x400) { in ov8858_apply_otp_r1a()
2495 ov8858_write_1byte(client, 0x5036, B_gain >> 8); in ov8858_apply_otp_r1a()
2496 ov8858_write_1byte(client, 0x5037, B_gain & 0x00ff); in ov8858_apply_otp_r1a()
2499 dev_dbg(&client->dev, "apply awb gain: 0x%x, 0x%x, 0x%x\n", in ov8858_apply_otp_r1a()
2504 if ((otp_ptr->flag & 0x10) && lsc_cfg->enable) { in ov8858_apply_otp_r1a()
2505 ov8858_read_1byte(client, 0x5000, &temp); in ov8858_apply_otp_r1a()
2506 temp = 0x80 | temp; in ov8858_apply_otp_r1a()
2507 ov8858_write_1byte(client, 0x5000, temp); in ov8858_apply_otp_r1a()
2508 for (i = 0; i < ARRAY_SIZE(otp_ptr->lenc); i++) { in ov8858_apply_otp_r1a()
2509 ov8858_write_1byte(client, 0x5800 + i, in ov8858_apply_otp_r1a()
2511 dev_dbg(&client->dev, "apply lenc[%d]: 0x%x\n", in ov8858_apply_otp_r1a()
2516 return 0; in ov8858_apply_otp_r1a()
2526 u32 golden_bg_ratio = 0; in ov8858_apply_otp_r2a()
2527 u32 golden_rg_ratio = 0; in ov8858_apply_otp_r2a()
2528 u32 golden_g_value = 0; in ov8858_apply_otp_r2a()
2534 golden_bg_ratio = awb_cfg->golden_b_value * 0x200 / golden_g_value; in ov8858_apply_otp_r2a()
2535 golden_rg_ratio = awb_cfg->golden_r_value * 0x200 / golden_g_value; in ov8858_apply_otp_r2a()
2539 if ((otp_ptr->flag & 0xC0) && golden_bg_ratio && golden_rg_ratio) { in ov8858_apply_otp_r2a()
2554 R_gain = 0x400 * R_gain / (base_gain); in ov8858_apply_otp_r2a()
2555 B_gain = 0x400 * B_gain / (base_gain); in ov8858_apply_otp_r2a()
2556 G_gain = 0x400 * G_gain / (base_gain); in ov8858_apply_otp_r2a()
2559 if (R_gain > 0x400) { in ov8858_apply_otp_r2a()
2560 ov8858_write_1byte(client, 0x5032, R_gain >> 8); in ov8858_apply_otp_r2a()
2561 ov8858_write_1byte(client, 0x5033, R_gain & 0x00ff); in ov8858_apply_otp_r2a()
2563 if (G_gain > 0x400) { in ov8858_apply_otp_r2a()
2564 ov8858_write_1byte(client, 0x5034, G_gain >> 8); in ov8858_apply_otp_r2a()
2565 ov8858_write_1byte(client, 0x5035, G_gain & 0x00ff); in ov8858_apply_otp_r2a()
2567 if (B_gain > 0x400) { in ov8858_apply_otp_r2a()
2568 ov8858_write_1byte(client, 0x5036, B_gain >> 8); in ov8858_apply_otp_r2a()
2569 ov8858_write_1byte(client, 0x5037, B_gain & 0x00ff); in ov8858_apply_otp_r2a()
2572 dev_dbg(&client->dev, "apply awb gain: 0x%x, 0x%x, 0x%x\n", in ov8858_apply_otp_r2a()
2577 if ((otp_ptr->flag & 0x10) && lsc_cfg->enable) { in ov8858_apply_otp_r2a()
2578 ov8858_read_1byte(client, 0x5000, &temp); in ov8858_apply_otp_r2a()
2579 temp = 0x80 | temp; in ov8858_apply_otp_r2a()
2580 ov8858_write_1byte(client, 0x5000, temp); in ov8858_apply_otp_r2a()
2581 for (i = 0; i < ARRAY_SIZE(otp_ptr->lenc); i++) { in ov8858_apply_otp_r2a()
2582 ov8858_write_1byte(client, 0x5800 + i, in ov8858_apply_otp_r2a()
2584 dev_dbg(&client->dev, "apply lenc[%d]: 0x%x\n", in ov8858_apply_otp_r2a()
2589 return 0; in ov8858_apply_otp_r2a()
2594 int ret = 0; in ov8858_apply_otp()
2641 int ret = 0; in ov8858_s_stream()
2656 if (ret < 0) { in ov8858_s_stream()
2684 int ret = 0; in ov8858_s_power()
2694 if (ret < 0) { in ov8858_s_power()
2738 if (ret < 0) in __ov8858_power_on()
2743 if (ret < 0) in __ov8858_power_on()
2748 if (ret < 0) { in __ov8858_power_on()
2754 gpiod_set_value_cansleep(ov8858->reset_gpio, 0); in __ov8858_power_on()
2757 if (ret < 0) { in __ov8858_power_on()
2773 return 0; in __ov8858_power_on()
2787 gpiod_set_value_cansleep(ov8858->pwdn_gpio, 0); in __ov8858_power_off()
2790 gpiod_set_value_cansleep(ov8858->reset_gpio, 0); in __ov8858_power_off()
2794 if (ret < 0) in __ov8858_power_off()
2799 //gpiod_set_value_cansleep(ov8858->power_gpio, 0); in __ov8858_power_off()
2821 return 0; in ov8858_runtime_suspend()
2829 v4l2_subdev_get_try_format(sd, fh->pad, 0); in ov8858_open()
2830 const struct ov8858_mode *def_mode = &supported_modes[0]; in ov8858_open()
2842 return 0; in ov8858_open()
2859 return 0; in ov8858_enum_frame_interval()
2884 return 0; in ov8858_g_mbus_config()
2932 int ret = 0; in ov8858_set_ctrl()
2947 return 0; in ov8858_set_ctrl()
2952 dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val); in ov8858_set_ctrl()
2959 dev_dbg(&client->dev, "set analog gain value 0x%x\n", ctrl->val); in ov8858_set_ctrl()
2971 dev_dbg(&client->dev, "set vb value 0x%x\n", ctrl->val); in ov8858_set_ctrl()
2981 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n", in ov8858_set_ctrl()
3012 0, 0, link_freq_menu_items); in ov8858_initialize_controls()
3017 0, ov8858->pixel_rate, 1, ov8858->pixel_rate); in ov8858_initialize_controls()
3045 0, 0, ov8858_test_pattern_menu); in ov8858_initialize_controls()
3056 return 0; in ov8858_initialize_controls()
3075 otp_flag = 0; in ov8858_otp_read_r1a()
3076 ov8858_read_1byte(client, 0x7010, &otp_flag); in ov8858_otp_read_r1a()
3077 if ((otp_flag & 0xc0) == 0x40) in ov8858_otp_read_r1a()
3078 addr = 0x7011; /* base address of info group 1 */ in ov8858_otp_read_r1a()
3079 else if ((otp_flag & 0x30) == 0x10) in ov8858_otp_read_r1a()
3080 addr = 0x7016; /* base address of info group 2 */ in ov8858_otp_read_r1a()
3081 else if ((otp_flag & 0x0c) == 0x04) in ov8858_otp_read_r1a()
3082 addr = 0x701b; /* base address of info group 3 */ in ov8858_otp_read_r1a()
3084 addr = 0; in ov8858_otp_read_r1a()
3086 if (addr != 0) { in ov8858_otp_read_r1a()
3087 otp_ptr->flag = 0x80; /* valid info in OTP */ in ov8858_otp_read_r1a()
3093 dev_dbg(dev, "fac info: module(0x%x) lens(0x%x) time(%d_%d_%d)!\n", in ov8858_otp_read_r1a()
3102 ov8858_read_1byte(client, 0x7020, &otp_flag); in ov8858_otp_read_r1a()
3103 if ((otp_flag & 0xc0) == 0x40) in ov8858_otp_read_r1a()
3104 addr = 0x7021; /* base address of info group 1 */ in ov8858_otp_read_r1a()
3105 else if ((otp_flag & 0x30) == 0x10) in ov8858_otp_read_r1a()
3106 addr = 0x7026; /* base address of info group 2 */ in ov8858_otp_read_r1a()
3107 else if ((otp_flag & 0x0c) == 0x04) in ov8858_otp_read_r1a()
3108 addr = 0x702b; /* base address of info group 3 */ in ov8858_otp_read_r1a()
3110 addr = 0; in ov8858_otp_read_r1a()
3112 if (addr != 0) { in ov8858_otp_read_r1a()
3113 otp_ptr->flag |= 0x40; /* valid info and AWB in OTP */ in ov8858_otp_read_r1a()
3117 ((temp >> 6) & 0x03); in ov8858_otp_read_r1a()
3120 ((temp >> 4) & 0x03); in ov8858_otp_read_r1a()
3123 ((temp >> 2) & 0x03); in ov8858_otp_read_r1a()
3126 ((temp) & 0x03); in ov8858_otp_read_r1a()
3127 dev_dbg(dev, "awb info: (0x%x, 0x%x, 0x%x, 0x%x)!\n", in ov8858_otp_read_r1a()
3133 ov8858_read_1byte(client, 0x7030, &otp_flag); in ov8858_otp_read_r1a()
3134 if ((otp_flag & 0xc0) == 0x40) in ov8858_otp_read_r1a()
3135 addr = 0x7031; /* base address of VCM Calibration group 1 */ in ov8858_otp_read_r1a()
3136 else if ((otp_flag & 0x30) == 0x10) in ov8858_otp_read_r1a()
3137 addr = 0x7034; /* base address of VCM Calibration group 2 */ in ov8858_otp_read_r1a()
3138 else if ((otp_flag & 0x0c) == 0x04) in ov8858_otp_read_r1a()
3139 addr = 0x7037; /* base address of VCM Calibration group 3 */ in ov8858_otp_read_r1a()
3141 addr = 0; in ov8858_otp_read_r1a()
3142 if (addr != 0) { in ov8858_otp_read_r1a()
3143 otp_ptr->flag |= 0x20; in ov8858_otp_read_r1a()
3147 ((temp >> 6) & 0x03); in ov8858_otp_read_r1a()
3150 ((temp >> 4) & 0x03); in ov8858_otp_read_r1a()
3151 otp_ptr->vcm_dir = (temp >> 2) & 0x03; in ov8858_otp_read_r1a()
3152 dev_dbg(dev, "vcm_info: 0x%x, 0x%x, 0x%x!\n", in ov8858_otp_read_r1a()
3159 ov8858_read_1byte(client, 0x703a, &otp_flag); in ov8858_otp_read_r1a()
3160 if ((otp_flag & 0xc0) == 0x40) in ov8858_otp_read_r1a()
3161 addr = 0x703b; /* base address of Lenc Calibration group 1 */ in ov8858_otp_read_r1a()
3162 else if ((otp_flag & 0x30) == 0x10) in ov8858_otp_read_r1a()
3163 addr = 0x70a9; /* base address of Lenc Calibration group 2 */ in ov8858_otp_read_r1a()
3164 else if ((otp_flag & 0x0c) == 0x04) in ov8858_otp_read_r1a()
3165 addr = 0x7117; /* base address of Lenc Calibration group 3 */ in ov8858_otp_read_r1a()
3167 addr = 0; in ov8858_otp_read_r1a()
3168 if (addr != 0) { in ov8858_otp_read_r1a()
3169 otp_ptr->flag |= 0x10; in ov8858_otp_read_r1a()
3170 for (i = 0; i < 110; i++) { in ov8858_otp_read_r1a()
3172 dev_dbg(dev, "lsc 0x%x!\n", otp_ptr->lenc[i]); in ov8858_otp_read_r1a()
3176 for (i = 0x7010; i <= 0x7184; i++) in ov8858_otp_read_r1a()
3177 ov8858_write_1byte(client, i, 0); /* clear OTP buffer */ in ov8858_otp_read_r1a()
3187 return 0; in ov8858_otp_read_r1a()
3202 otp_flag = 0; in ov8858_otp_read_r2a()
3203 ov8858_read_1byte(client, 0x7010, &otp_flag); in ov8858_otp_read_r2a()
3204 if ((otp_flag & 0xc0) == 0x40) in ov8858_otp_read_r2a()
3205 addr = 0x7011; /* base address of info group 1 */ in ov8858_otp_read_r2a()
3206 else if ((otp_flag & 0x30) == 0x10) in ov8858_otp_read_r2a()
3207 addr = 0x7019; /* base address of info group 2 */ in ov8858_otp_read_r2a()
3209 addr = 0; in ov8858_otp_read_r2a()
3211 if (addr != 0) { in ov8858_otp_read_r2a()
3212 otp_ptr->flag = 0xC0; /* valid info and AWB in OTP */ in ov8858_otp_read_r2a()
3221 ((temp >> 6) & 0x03); in ov8858_otp_read_r2a()
3224 ((temp >> 4) & 0x03); in ov8858_otp_read_r2a()
3226 dev_dbg(dev, "fac info: module(0x%x) lens(0x%x) time(%d_%d_%d) !\n", in ov8858_otp_read_r2a()
3232 dev_dbg(dev, "awb info: (0x%x, 0x%x)!\n", in ov8858_otp_read_r2a()
3238 ov8858_read_1byte(client, 0x7021, &otp_flag); in ov8858_otp_read_r2a()
3239 if ((otp_flag & 0xc0) == 0x40) in ov8858_otp_read_r2a()
3240 addr = 0x7022; /* base address of VCM Calibration group 1 */ in ov8858_otp_read_r2a()
3241 else if ((otp_flag & 0x30) == 0x10) in ov8858_otp_read_r2a()
3242 addr = 0x7025; /* base address of VCM Calibration group 2 */ in ov8858_otp_read_r2a()
3244 addr = 0; in ov8858_otp_read_r2a()
3246 if (addr != 0) { in ov8858_otp_read_r2a()
3247 otp_ptr->flag |= 0x20; in ov8858_otp_read_r2a()
3251 ((temp >> 6) & 0x03); in ov8858_otp_read_r2a()
3254 ((temp >> 4) & 0x03); in ov8858_otp_read_r2a()
3255 otp_ptr->vcm_dir = (temp >> 2) & 0x03; in ov8858_otp_read_r2a()
3259 ov8858_read_1byte(client, 0x7028, &otp_flag); in ov8858_otp_read_r2a()
3260 if ((otp_flag & 0xc0) == 0x40) in ov8858_otp_read_r2a()
3261 addr = 0x7029; /* base address of Lenc Calibration group 1 */ in ov8858_otp_read_r2a()
3262 else if ((otp_flag & 0x30) == 0x10) in ov8858_otp_read_r2a()
3263 addr = 0x711a; /* base address of Lenc Calibration group 2 */ in ov8858_otp_read_r2a()
3265 addr = 0; in ov8858_otp_read_r2a()
3267 if (addr != 0) { in ov8858_otp_read_r2a()
3268 checksum = 0; in ov8858_otp_read_r2a()
3269 for (i = 0; i < 240; i++) { in ov8858_otp_read_r2a()
3272 dev_dbg(dev, "lsc_info: 0x%x!\n", otp_ptr->lenc[i]); in ov8858_otp_read_r2a()
3277 otp_ptr->flag |= 0x10; in ov8858_otp_read_r2a()
3280 for (i = 0x7010; i <= 0x720a; i++) in ov8858_otp_read_r2a()
3281 ov8858_write_1byte(client, i, 0); /* clear OTP buffer */ in ov8858_otp_read_r2a()
3291 return 0; in ov8858_otp_read_r2a()
3296 int temp = 0; in ov8858_otp_read()
3297 int ret = 0; in ov8858_otp_read()
3305 ov8858_read_1byte(client, 0x5002, &temp); in ov8858_otp_read()
3306 ov8858_write_1byte(client, 0x5002, (temp & (~0x08))); in ov8858_otp_read()
3309 ov8858_write_1byte(client, 0x3d84, 0xC0); in ov8858_otp_read()
3310 ov8858_write_1byte(client, 0x3d88, 0x70); /* OTP start address */ in ov8858_otp_read()
3311 ov8858_write_1byte(client, 0x3d89, 0x10); in ov8858_otp_read()
3313 ov8858_write_1byte(client, 0x3d8A, 0x72); /* OTP end address */ in ov8858_otp_read()
3314 ov8858_write_1byte(client, 0x3d8B, 0x0a); in ov8858_otp_read()
3316 ov8858_write_1byte(client, 0x3d8A, 0x71); /* OTP end address */ in ov8858_otp_read()
3317 ov8858_write_1byte(client, 0x3d8B, 0x84); in ov8858_otp_read()
3319 ov8858_write_1byte(client, 0x3d81, 0x01); /* load otp into buffer */ in ov8858_otp_read()
3327 /* set 0x5002[3] to "1" */ in ov8858_otp_read()
3328 ov8858_read_1byte(client, 0x5002, &temp); in ov8858_otp_read()
3329 ov8858_write_1byte(client, 0x5002, 0x08 | (temp & (~0x08))); in ov8858_otp_read()
3343 u32 id = 0; in ov8858_check_sensor_id()
3359 dev_info(dev, "Detected OV%06x sensor, REVISION 0x%x\n", CHIP_ID, id); in ov8858_check_sensor_id()
3364 ov8858->cur_mode = &supported_modes_r2a_4lane[0]; in ov8858_check_sensor_id()
3369 ov8858->cur_mode = &supported_modes_r2a_2lane[0]; in ov8858_check_sensor_id()
3378 ov8858->cur_mode = &supported_modes_r1a_4lane[0]; in ov8858_check_sensor_id()
3383 ov8858->cur_mode = &supported_modes_r1a_2lane[0]; in ov8858_check_sensor_id()
3392 return 0; in ov8858_check_sensor_id()
3399 for (i = 0; i < OV8858_NUM_SUPPLIES; i++) in ov8858_configure_regulators()
3420 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0); in ov8858_parse_of()
3421 if (rval <= 0) { in ov8858_parse_of()
3428 ov8858->cur_mode = &supported_modes_r2a_4lane[0]; in ov8858_parse_of()
3437 ov8858->cur_mode = &supported_modes_r2a_2lane[0]; in ov8858_parse_of()
3446 return 0; in ov8858_parse_of()
3461 (DRIVER_VERSION & 0xff00) >> 8, in ov8858_probe()
3462 DRIVER_VERSION & 0x00ff); in ov8858_probe()
3508 if (ret != 0) in ov8858_probe()
3553 if (ret < 0) in ov8858_probe()
3557 memset(facing, 0, sizeof(facing)); in ov8858_probe()
3558 if (strcmp(ov8858->module_facing, "back") == 0) in ov8858_probe()
3559 facing[0] = 'b'; in ov8858_probe()
3561 facing[0] = 'f'; in ov8858_probe()
3576 return 0; in ov8858_probe()
3613 return 0; in ov8858_remove()
3625 { "ovti,ov8858", 0 },