Lines Matching refs:I2C_DEV_DES
96 I2C_DEV_DES = 0, enumerator
201 { I2C_DEV_DES, 2, 0x0006, 0x00, 0x00, 0x00 }, // Link A/B/C/D: select GMSL1, Disabled
203 { I2C_DEV_DES, 2, 0x040B, 0x00, 0x00, 0x00 }, // CSI_OUT_EN=0, CSI output disabled
205 { I2C_DEV_DES, 2, 0x06C2, 0x10, 0x00, 0x0a }, // Increase CMU voltage to for wide temperature range
207 { I2C_DEV_DES, 2, 0x14D1, 0x03, 0x00, 0x00 }, // VGAHiGain
208 { I2C_DEV_DES, 2, 0x15D1, 0x03, 0x00, 0x00 }, // VGAHiGain
209 { I2C_DEV_DES, 2, 0x16D1, 0x03, 0x00, 0x00 }, // VGAHiGain
210 { I2C_DEV_DES, 2, 0x17D1, 0x03, 0x00, 0x0a }, // VGAHiGain
212 { I2C_DEV_DES, 2, 0x1445, 0x00, 0x00, 0x00 }, // Disable SSC
213 { I2C_DEV_DES, 2, 0x1545, 0x00, 0x00, 0x00 }, // Disable SSC
214 { I2C_DEV_DES, 2, 0x1645, 0x00, 0x00, 0x00 }, // Disable SSC
215 { I2C_DEV_DES, 2, 0x1745, 0x00, 0x00, 0x0a }, // Disable SSC
217 { I2C_DEV_DES, 2, 0x0B07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific)
218 { I2C_DEV_DES, 2, 0x0C07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific)
219 { I2C_DEV_DES, 2, 0x0D07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific)
220 { I2C_DEV_DES, 2, 0x0E07, 0x84, 0x00, 0x00 }, // Enable HVEN and DBL (application specific)
221 …{ I2C_DEV_DES, 2, 0x0B0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required whe…
222 …{ I2C_DEV_DES, 2, 0x0C0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required whe…
223 …{ I2C_DEV_DES, 2, 0x0D0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required whe…
224 …{ I2C_DEV_DES, 2, 0x0E0F, 0x01, 0x00, 0x00 }, // Disable processing HS and DE signals(required whe…
226 { I2C_DEV_DES, 2, 0x090B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
227 { I2C_DEV_DES, 2, 0x092D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
229 { I2C_DEV_DES, 2, 0x090D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
230 { I2C_DEV_DES, 2, 0x090E, 0x1e, 0x00, 0x00 }, // DST0 VC = 0, DT = YUV422 8bit
231 { I2C_DEV_DES, 2, 0x090F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
232 { I2C_DEV_DES, 2, 0x0910, 0x00, 0x00, 0x00 }, // DST1 VC = 0, DT = Frame Start
233 { I2C_DEV_DES, 2, 0x0911, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
234 { I2C_DEV_DES, 2, 0x0912, 0x01, 0x00, 0x00 }, // DST2 VC = 0, DT = Frame End
236 { I2C_DEV_DES, 2, 0x094B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
237 { I2C_DEV_DES, 2, 0x096D, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
239 { I2C_DEV_DES, 2, 0x094D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
240 { I2C_DEV_DES, 2, 0x094E, 0x5e, 0x00, 0x00 }, // DST0 VC = 1, DT = YUV422 8bit
241 { I2C_DEV_DES, 2, 0x094F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
242 { I2C_DEV_DES, 2, 0x0950, 0x40, 0x00, 0x00 }, // DST1 VC = 1, DT = Frame Start
243 { I2C_DEV_DES, 2, 0x0951, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
244 { I2C_DEV_DES, 2, 0x0952, 0x41, 0x00, 0x00 }, // DST2 VC = 1, DT = Frame End
246 { I2C_DEV_DES, 2, 0x098B, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
247 { I2C_DEV_DES, 2, 0x09AD, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
249 { I2C_DEV_DES, 2, 0x098D, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
250 { I2C_DEV_DES, 2, 0x098E, 0x9e, 0x00, 0x00 }, // DST0 VC = 2, DT = YUV422 8bit
251 { I2C_DEV_DES, 2, 0x098F, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
252 { I2C_DEV_DES, 2, 0x0990, 0x80, 0x00, 0x00 }, // DST1 VC = 2, DT = Frame Start
253 { I2C_DEV_DES, 2, 0x0991, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
254 { I2C_DEV_DES, 2, 0x0992, 0x81, 0x00, 0x00 }, // DST2 VC = 2, DT = Frame End
256 { I2C_DEV_DES, 2, 0x09CB, 0x07, 0x00, 0x00 }, // Enable 0/1/2 SRC/DST Mappings
257 { I2C_DEV_DES, 2, 0x09ED, 0x15, 0x00, 0x00 }, // SRC/DST 0/1/2 -> CSI2 Controller 1;
259 { I2C_DEV_DES, 2, 0x09CD, 0x1e, 0x00, 0x00 }, // SRC0 VC = 0, DT = YUV422 8bit
260 { I2C_DEV_DES, 2, 0x09CE, 0xde, 0x00, 0x00 }, // DST0 VC = 3, DT = YUV422 8bit
261 { I2C_DEV_DES, 2, 0x09CF, 0x00, 0x00, 0x00 }, // SRC1 VC = 0, DT = Frame Start
262 { I2C_DEV_DES, 2, 0x09D0, 0xc0, 0x00, 0x00 }, // DST1 VC = 3, DT = Frame Start
263 { I2C_DEV_DES, 2, 0x09D1, 0x01, 0x00, 0x00 }, // SRC2 VC = 0, DT = Frame End
264 { I2C_DEV_DES, 2, 0x09D2, 0xc1, 0x00, 0x00 }, // DST2 VC = 3, DT = Frame End
266 { I2C_DEV_DES, 2, 0x08A0, 0x24, 0x00, 0x00 }, // DPHY0 enabled as clock, MIPI PHY Mode: 2x4 mode
268 { I2C_DEV_DES, 2, 0x08A3, 0xe4, 0x00, 0x00 }, // PHY1 D1->D3, D0->D2; PHY0 D1->D1, D0->D0
270 { I2C_DEV_DES, 2, 0x090A, 0xc0, 0x00, 0x00 }, // MIPI PHY 0: 4 lanes, DPHY, 2bit VC
271 { I2C_DEV_DES, 2, 0x094A, 0xc0, 0x00, 0x00 }, // MIPI PHY 1: 4 lanes, DPHY, 2bit VC
273 { I2C_DEV_DES, 2, 0x08A2, 0x34, 0x00, 0x00 }, // Enable MIPI PHY 0/1, t_lpx = 106.7ns
275 …{ I2C_DEV_DES, 2, 0x040B, 0x40, 0x00, 0x00 }, // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-…
276 { I2C_DEV_DES, 2, 0x040C, 0x00, 0x00, 0x00 }, // pipe 0 and 1 VC software override: 0x00
277 { I2C_DEV_DES, 2, 0x040D, 0x00, 0x00, 0x00 }, // pipe 2 and 3 VC software override: 0x00
278 { I2C_DEV_DES, 2, 0x040E, 0x5e, 0x00, 0x00 }, // pipe 0 DT=0x1E: YUV422 8-bit
279 { I2C_DEV_DES, 2, 0x040F, 0x7e, 0x00, 0x00 }, // pipe 1 DT=0x1E: YUV422 8-bit
280 { I2C_DEV_DES, 2, 0x0410, 0x7a, 0x00, 0x00 }, // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit
281 …{ I2C_DEV_DES, 2, 0x0411, 0x48, 0x00, 0x00 }, // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-…
282 …{ I2C_DEV_DES, 2, 0x0412, 0x20, 0x00, 0x00 }, // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2…
283 { I2C_DEV_DES, 2, 0x0415, 0xc0, 0xc0, 0x00 }, // pipe 0/1 enable software overide
284 { I2C_DEV_DES, 2, 0x0418, 0xc0, 0xc0, 0x00 }, // pipe 2/3 enable software overide
285 { I2C_DEV_DES, 2, 0x041A, 0xf0, 0x00, 0x00 }, // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode
287 …{ I2C_DEV_DES, 2, 0x0003, 0xaa, 0x00, 0x00 }, // Enable Remote Control Channel Link A/B/C/D for Po…
288 { I2C_DEV_DES, 2, 0x0006, 0x0f, 0x00, 0x64 }, // Enable all links and pipes
313 { I2C_DEV_DES, 2, REG_NULL, 0x00, 0x00, 0x00 },
509 ret = max96722_read_reg(max96722, I2C_DEV_DES, in max96722_check_local_chipid()
581 max96722_read_reg(max96722, I2C_DEV_DES, in max96722_get_link_lock_state()
590 max96722_read_reg(max96722, I2C_DEV_DES, in max96722_get_link_lock_state()
603 max96722_read_reg(max96722, I2C_DEV_DES, in max96722_get_link_lock_state()
612 max96722_read_reg(max96722, I2C_DEV_DES, in max96722_get_link_lock_state()
625 max96722_read_reg(max96722, I2C_DEV_DES, in max96722_get_link_lock_state()
634 max96722_read_reg(max96722, I2C_DEV_DES, in max96722_get_link_lock_state()
647 max96722_read_reg(max96722, I2C_DEV_DES, in max96722_get_link_lock_state()
656 max96722_read_reg(max96722, I2C_DEV_DES, in max96722_get_link_lock_state()
683 max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
685 max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
689 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
695 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
701 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
704 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
710 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
715 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
720 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
725 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
732 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
737 max96722_write_reg(max96722, I2C_DEV_DES, in max96722_check_link_lock_state()
816 ret = max96722_read_reg(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
837 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
841 ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
844 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
852 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
856 ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
859 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
867 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
871 ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
874 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
882 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
886 ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
889 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
902 max96722, I2C_DEV_DES, in max96722_dphy_dpll_predef_set()
923 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_auto_init_deskew()
928 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_auto_init_deskew()
933 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_auto_init_deskew()
938 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_auto_init_deskew()
962 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_frame_sync_period()
966 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_frame_sync_period()
969 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_frame_sync_period()
982 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_frame_sync_period()
986 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_frame_sync_period()
990 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_frame_sync_period()
995 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_frame_sync_period()
1001 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_frame_sync_period()
1014 ret |= max96722_write_reg(max96722, I2C_DEV_DES, in max96722_frame_sync_period()
1028 ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_mipi_enable()
1032 ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_mipi_enable()
1037 ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_mipi_enable()
1041 ret |= max96722_update_reg_bits(max96722, I2C_DEV_DES, in max96722_mipi_enable()
1930 max96722->i2c_addr[I2C_DEV_DES] = client->addr; in max96722_probe()