Lines Matching refs:it66353_h2swwr
436 u8 it66353_h2swwr(u8 offset, u8 wdata) in it66353_h2swwr() function
634 it66353_h2swwr(0x3D, 0x09); // DDC FIFO Clear in _tx_scdc_write()
635 it66353_h2swwr(0x3E, 0xA8); // EDID Address in _tx_scdc_write()
636 it66353_h2swwr(0x3F, offset); // EDID Offset in _tx_scdc_write()
637 it66353_h2swwr(0x40, 0x01); // ByteNum[7:0] in _tx_scdc_write()
638 it66353_h2swwr(0x42, wdata); // WrData in _tx_scdc_write()
639 it66353_h2swwr(0x3D, 0x01); // Sequential Burst Write in _tx_scdc_write()
641 it66353_h2swwr(0x3C, reg3C); // Disable PC DDC Mode in _tx_scdc_write()
668 it66353_h2swwr(0x3D, 0x09); // DDC FIFO Clear in _tx_scdc_read()
669 it66353_h2swwr(0x3E, 0xA8); // EDID Address in _tx_scdc_read()
670 it66353_h2swwr(0x3F, offset); // EDID Offset in _tx_scdc_read()
671 it66353_h2swwr(0x40, 0x01); // ByteNum[7:0] in _tx_scdc_read()
673 it66353_h2swwr(0x3D, 0x00); // Sequential Burst Write in _tx_scdc_read()
675 it66353_h2swwr(0x3C, reg3C); // Disable PC DDC Mode in _tx_scdc_read()
702 it66353_h2swwr(0x3D, 0x09); // DDC FIFO Clear in _tx_hdcp_write()
703 it66353_h2swwr(0x3E, 0x74); // EDID Address in _tx_hdcp_write()
704 it66353_h2swwr(0x3F, offset); // EDID Offset in _tx_hdcp_write()
705 it66353_h2swwr(0x40, 0x01); // ByteNum[7:0] in _tx_hdcp_write()
706 it66353_h2swwr(0x42, data); // WrData in _tx_hdcp_write()
707 it66353_h2swwr(0x3D, 0x01); // Sequential Burst Write in _tx_hdcp_write()
734 it66353_h2swwr(0x3D, 0x09); // DDC FIFO Clear in _tx_hdcp_read()
735 it66353_h2swwr(0x3E, 0x74); // EDID Address in _tx_hdcp_read()
736 it66353_h2swwr(0x3F, offset); // EDID Offset in _tx_hdcp_read()
737 it66353_h2swwr(0x40, len); // ByteNum[7:0] in _tx_hdcp_read()
739 it66353_h2swwr(0x3D, 0x00); // Sequential Burst Write in _tx_hdcp_read()
772 it66353_h2swwr(0x3D, 0x09); // DDC FIFO Clear in _tx_scdc_read_ced()
773 it66353_h2swwr(0x3E, 0xA8); // EDID Address in _tx_scdc_read_ced()
774 it66353_h2swwr(0x3F, 0x50); // EDID Offset in _tx_scdc_read_ced()
775 it66353_h2swwr(0x40, 0x06); // ByteNum[7:0] in _tx_scdc_read_ced()
777 it66353_h2swwr(0x3D, 0x00); // Sequential Burst Write in _tx_scdc_read_ced()
824 it66353_h2swwr(0xAD, 0xFF); // clear CED valid on 0xB0 in _tx_show_sink_ced()
940 it66353_h2swwr(0x1C, count); in it66353_sw_config_timer0()
1515 it66353_h2swwr(0x30 + port * 2, 0xff); in _sw_int_enable()
1519 it66353_h2swwr(0x30 + port * 2, 0x00); in _sw_int_enable()
1521 it66353_h2swwr(0x20 + port * 2, 0xff); in _sw_int_enable()
1522 it66353_h2swwr(0x21 + port * 2, 0xff); in _sw_int_enable()
1553 it66353_h2swwr(0x1D, count); in _sw_config_timer1()
1598 it66353_h2swwr(0xAD, 0xFF); in _sw_reset_scdc_monitor()
1623 it66353_h2swwr(0xB0, 0xC0); in it66353_sw_clear_hdcp_status()
1682 it66353_h2swwr(0xAB, 0x60); in _sw_hdcp_access_enable()
1685 it66353_h2swwr(0xAB, 0x74); in _sw_hdcp_access_enable()
1694 it66353_h2swwr(0xFF, 0xC3); in _tx_init()
1695 it66353_h2swwr(0xFF, 0xA5); in _tx_init()
1697 it66353_h2swwr(0xFF, 0xFF); in _tx_init()
1709 it66353_h2swwr(0x27, 0xff); in _tx_init()
1775 it66353_h2swwr(0xEF, it66353_gdev.opts.dev_opt->RxAddr | 0x01); in _sw_init()
1782 it66353_h2swwr(0xEE, (it66353_gdev.opts.dev_opt->CecAddr | 0x01)); in _sw_init()
1791 it66353_h2swwr(0xEE, (it66353_gdev.opts.dev_opt->CecAddr | 0x01)); in _sw_init()
1795 it66353_h2swwr(0xEE, (it66353_gdev.opts.dev_opt->CecAddr & 0xFE)); in _sw_init()
1873 it66353_h2swwr(0xB0, 0x80); in _sw_init()
1881 it66353_h2swwr(0xEF, it66353_gdev.opts.dev_opt->RxAddr | 0x01); in _sw_reset()
1921 it66353_h2swwr(0x1E, timer_int); in it66353_cal_rclk()
1922 it66353_h2swwr(0x1F, timer_flt); in it66353_cal_rclk()
1929 it66353_h2swwr(0x2D, (u8)wclk_valid_num & 0xFF); in it66353_cal_rclk()
1934 it66353_h2swwr(0x2E, (wclk_high_ext << 6) + ((u8)wclk_high_num_b)); in it66353_cal_rclk()
1939 it66353_h2swwr(0x2F, (wclk_high_ext << 6) + ((u8)wclk_high_num_c)); in it66353_cal_rclk()
1956 it66353_h2swwr(0x1e, 0x14); in it66353_init_rclk()
1957 it66353_h2swwr(0x1f, 0x00); in it66353_init_rclk()
1959 it66353_h2swwr(0x2d, 0x80); in it66353_init_rclk()
1960 it66353_h2swwr(0x2e, 0x11); in it66353_init_rclk()
1961 it66353_h2swwr(0x2f, 0x87); in it66353_init_rclk()
1966 it66353_h2swwr(0x1e, 0x13); in it66353_init_rclk()
1967 it66353_h2swwr(0x1f, 0x91); in it66353_init_rclk()
1969 it66353_h2swwr(0x2d, 0x7d); in it66353_init_rclk()
1970 it66353_h2swwr(0x2e, 0x50); in it66353_init_rclk()
1971 it66353_h2swwr(0x2f, 0x47); in it66353_init_rclk()
1976 it66353_h2swwr(0x1e, 0x12); in it66353_init_rclk()
1977 it66353_h2swwr(0x1f, 0x90); in it66353_init_rclk()
1979 it66353_h2swwr(0x2d, 0x77); in it66353_init_rclk()
1980 it66353_h2swwr(0x2e, 0x10); in it66353_init_rclk()
1981 it66353_h2swwr(0x2f, 0xc6); in it66353_init_rclk()
2110 it66353_h2swwr(0x20 + port * 2, sw_reg20); in it66353_get_rx_vclk()
2226 it66353_h2swwr(0x20 + port * 2, sw_reg20); in it66353_detect_port()
2230 it66353_h2swwr(0x21 + port * 2, sw_reg21); in it66353_detect_port()
2389 it66353_h2swwr(0x20 + port * 2, sw_reg20); in it66353_sw_irq()
2390 it66353_h2swwr(0x21 + port * 2, sw_reg21); in it66353_sw_irq()
2506 it66353_h2swwr(0x27, sw_reg27); in it66353_tx_irq()
2507 it66353_h2swwr(0x28, sw_reg28); in it66353_tx_irq()
2552 it66353_h2swwr(0x3D, 0x0A); // Generate SCL Clock in it66353_tx_irq()
2553 it66353_h2swwr(0x3C, reg3C); in it66353_tx_irq()
2570 it66353_h2swwr(0x3D, 0x0F); in it66353_tx_irq()
2571 it66353_h2swwr(0x3C, reg3C); in it66353_tx_irq()
2581 it66353_h2swwr(0x3D, 0x09); in it66353_tx_irq()
2582 it66353_h2swwr(0x3C, reg3C); in it66353_tx_irq()
3613 it66353_h2swwr(0x3D, 0x09); // DDC FIFO Clear in it66353_read_edid()
3614 it66353_h2swwr(0x3E, 0xA0); // EDID Address in it66353_read_edid()
3615 it66353_h2swwr(0x3F, offset); // EDID Offset in it66353_read_edid()
3616 it66353_h2swwr(0x40, length); // Read ByteNum[7:0] in it66353_read_edid()
3617 it66353_h2swwr(0x41, block/2); // EDID Segment in it66353_read_edid()
3620 it66353_h2swwr(0x3D, 0x03); // EDID Read Fire in it66353_read_edid()
3638 it66353_h2swwr(0x3C, reg3C); // restore PC DDC Mode in it66353_read_edid()
3773 it66353_h2swwr(0xe9, it66353_gdev.vars.VSDBOffset); // VSDB_Offset in it66353_setup_edid_ram_step2()
3789 it66353_h2swwr(0xd9 + i * 2, phyAB); // Port0 VSDB_AB in it66353_setup_edid_ram_step2()
3790 it66353_h2swwr(0xda + i * 2, phyCD); // Port0 VSDB_CD in it66353_setup_edid_ram_step2()
3814 it66353_h2swwr(0xe2 + i * 2, (u8)sum); in it66353_setup_edid_ram_step2()
3860 it66353_h2swwr(0x3D, 0x0F); in it66353_ddc_abort()
3875 it66353_h2swwr(0x3D, 0x0A); in it66353_ddc_abort()
3876 it66353_h2swwr(0x3D, 0x09); in it66353_ddc_abort()
3877 it66353_h2swwr(0x3C, reg3C); in it66353_ddc_abort()
4220 it66353_h2swwr(0x3D, 0x09); // DDC FIFO Clear in it66353_write_edid()
4221 it66353_h2swwr(0x3E, 0xA0); // EDID Address in it66353_write_edid()
4222 it66353_h2swwr(0x3F, offset); // EDID Offset in it66353_write_edid()
4223 it66353_h2swwr(0x40, length); // Read ByteNum[7:0] in it66353_write_edid()
4224 it66353_h2swwr(0x41, segment / 2); // EDID Segment in it66353_write_edid()
4227 it66353_h2swwr(0x42, *data_buffer); in it66353_write_edid()
4232 it66353_h2swwr(0x3D, 0x07); // EDID Write Fire in it66353_write_edid()
4240 it66353_h2swwr(0x3C, reg3C); // restore PC DDC Mode in it66353_write_edid()