Lines Matching refs:it66353_h2swset
450 u8 it66353_h2swset(u8 offset, u8 mask, u8 wdata) in it66353_h2swset() function
633 it66353_h2swset(0x3C, 0x01, 0x01); // Enable PC DDC Mode in _tx_scdc_write()
667 it66353_h2swset(0x3C, 0x01, 0x01); // Enable PC DDC Mode in _tx_scdc_read()
701 it66353_h2swset(0x3C, 0x01, 0x01); // Enable PC DDC Mode in _tx_hdcp_write()
709 it66353_h2swset(0x3C, 0x01, 0x00); // Disable PC DDC Mode in _tx_hdcp_write()
733 it66353_h2swset(0x3C, 0x01, 0x01); // Enable PC DDC Mode in _tx_hdcp_read()
741 it66353_h2swset(0x3C, 0x01, 0x00); // Disable PC DDC Mode in _tx_hdcp_read()
771 it66353_h2swset(0x3C, 0x01, 0x01); // Enable PC DDC Mode in _tx_scdc_read_ced()
779 it66353_h2swset(0x3C, 0x01, 0x00); // Disable PC DDC Mode in _tx_scdc_read_ced()
795 it66353_h2swset(0xD3, 0x80, 0x00); in _tx_power_down()
796 it66353_h2swset(0xD1, 0x60, 0x60); in _tx_power_down()
802 it66353_h2swset(0xD3, 0x80, 0x80); // Reg_XP_ALPWDB=1 in _tx_power_on()
803 it66353_h2swset(0xD1, 0x60, 0x00); // Reg_XP_PWDi = 0, Reg_XP_PWDPLL=0 in _tx_power_on()
820 it66353_h2swset(0xAC, 0xE0, (i<<5)); // offset select in _tx_show_sink_ced()
862 it66353_h2swset(0xB2, 0x03, 0x00); in _tx_ovwr_hdmi_clk()
865 it66353_h2swset(0xB2, 0x03, 0x01); in _tx_ovwr_hdmi_clk()
868 it66353_h2swset(0xB2, 0x03, 0x03); in _tx_ovwr_hdmi_clk()
879 it66353_h2swset(0xB2, 0x0C, 0x00); in _tx_ovwr_h20_scrb()
882 it66353_h2swset(0xB2, 0x0C, 0x08); in _tx_ovwr_h20_scrb()
885 it66353_h2swset(0xB2, 0x0C, 0x0c); in _tx_ovwr_h20_scrb()
906 it66353_h2swset(0x51 + port, 0x28, 0x00); in it66353it66353_rx_ovwr_hdmi_clk()
909 it66353_h2swset(0x51 + port, 0x28, 0x20); in it66353it66353_rx_ovwr_hdmi_clk()
912 it66353_h2swset(0x51 + port, 0x28, 0x28); in it66353it66353_rx_ovwr_hdmi_clk()
923 it66353_h2swset(0x51 + port, 0x30, 0x00); in it66353it66353_rx_ovwr_h20_scrb()
926 it66353_h2swset(0x51 + port, 0x30, 0x20); in it66353it66353_rx_ovwr_h20_scrb()
929 it66353_h2swset(0x51 + port, 0x30, 0x30); in it66353it66353_rx_ovwr_h20_scrb()
945 it66353_h2swset(0x38, 0x02, 0x02); in it66353it66353_sw_enable_timer0()
950 it66353_h2swset(0x28, 0x02, 0x02); in _sw_clear_timer0_interrupt()
998 it66353_h2swset(0xB2, 0x0F, 0x00); in _tx_ovwr_hdmi_mode()
1001 it66353_h2swset(0xB2, 0x0F, 0x05); in _tx_ovwr_hdmi_mode()
1004 it66353_h2swset(0xB2, 0x0F, 0x0F); in _tx_ovwr_hdmi_mode()
1021 it66353_h2swset(0xD1, 0x07, 0x04); in _tx_setup_afe()
1023 it66353_h2swset(0xD1, 0x07, 0x03); in _tx_setup_afe()
1033 it66353_h2swset(0xd8, 0xf0, 0x00); in _tx_setup_afe()
1044 it66353_h2swset(0xd8, 0xf0, 0x30); in _tx_setup_afe()
1067 it66353_h2swset(0xD0, 0x08, (H2ON_PLL << 3)); in _tx_setup_afe()
1068 it66353_h2swset(0xD3, 0x1F, DRV_ISW); in _tx_setup_afe()
1069 it66353_h2swset(0xD4, 0xF4, (DRV_PISWC << 6)+(DRV_PISW << 4)+(DRV_HS << 2)); in _tx_setup_afe()
1070 it66353_h2swset(0xD5, 0xBF, (DRV_NOPE << 7) + (DRV_TERMON << 5) + DRV_RTERM); in _tx_setup_afe()
1071 it66353_h2swset(0xD7, 0x1F, DRV_ISWC); in _tx_setup_afe()
1072 it66353_h2swset(0xD6, 0x0F, DRV_TPRE); in _tx_setup_afe()
1098 it66353_h2swset(0x05, 0x01, 0x01); in it66353_rx_caof_init()
1099 it66353_h2swset(0x59 + port, 0x20, 0x20); // new at IT6635B0 in it66353_rx_caof_init()
1100 it66353_h2swset(0x05 + port, 0x01, 0x01); // IPLL RST, it6635 in it66353_rx_caof_init()
1158 it66353_h2swset(0x59+port, 0x20, 0x00); in it66353_rx_caof_init()
1159 it66353_h2swset(0x05+port, 0x01, 0x00); in it66353_rx_caof_init()
1160 it66353_h2swset(0x05, 0x01, 0x00); in it66353_rx_caof_init()
1296 it66353_h2swset(0x16, mask, mask); in _rx_wdog_rst()
1298 it66353_h2swset(0x16, mask, 0x00); in _rx_wdog_rst()
1300 it66353_h2swset(0x2b, 0x01, 0x00); in _rx_wdog_rst()
1303 it66353_h2swset(0x2b, 0x01, 0x01); in _rx_wdog_rst()
1312 it66353_h2swset(0x51 + port, 0x38, 0x00); in _rx_ovwr_hdmi_mode()
1313 it66353_h2swset(0x98 + port, 0xC0, 0x00); in _rx_ovwr_hdmi_mode()
1316 it66353_h2swset(0x51 + port, 0x38, 0x20); in _rx_ovwr_hdmi_mode()
1317 it66353_h2swset(0x98 + port, 0xC0, 0x00); in _rx_ovwr_hdmi_mode()
1320 it66353_h2swset(0x51 + port, 0x38, 0x38); in _rx_ovwr_hdmi_mode()
1321 it66353_h2swset(0x98 + port, 0xC0, 0xC0); in _rx_ovwr_hdmi_mode()
1361 it66353_h2swset(0x3C, 0x01, 0x01); in _rx_set_hpd()
1363 it66353_h2swset(0x3C, 0x01, 0x00); in _rx_set_hpd()
1372 it66353_h2swset(0x4C + port, 0xC0, 0x40);// RXHPD=0 in _rx_set_hpd()
1374 it66353_h2swset(0x4C + port, 0xC0, 0xC0);// RXHPD=1 in _rx_set_hpd()
1404 it66353_h2swset(0x4C + port, 0xC0, 0xC0);// RXHPD=1 in _rx_set_hpd()
1406 it66353_h2swset(0x4C + port, 0xC0, 0x40);// RXHPD=0 in _rx_set_hpd()
1410 it66353_h2swset(0xB2, 0x0A, 0x0A); // clear H2Mode in _rx_set_hpd()
1489 it66353_h2swset(0x90 + port, 0x3D, 0x1D); in it66353_rx_auto_power_down_enable()
1491 it66353_h2swset(0x90 + port, 0x3D, 0x00); in it66353_rx_auto_power_down_enable()
1507 it66353_h2swset(0x88 + port, 0xFF, channel); in it66353_rx_term_power_down()
1516 it66353_h2swset(0x31 + port * 2, 0x01, 0x01); in _sw_int_enable()
1520 it66353_h2swset(0x31 + port * 2, 0x01, 0x00); in _sw_int_enable()
1538 it66353_h2swset(0x38, 0x02, 0x00); in it66353_sw_disable_timer0()
1558 it66353_h2swset(0x38, 0x04, 0x04); in _sw_enable_timer1()
1563 it66353_h2swset(0x38, 0x04, 0x00); in _sw_disable_timer1()
1573 it66353_h2swset(0x28, 0x04, 0x04); in _sw_clear_timer1_interrupt()
1659 it66353_h2swset(0x2A, reg70, reg70); in _sw_sdi_check()
1696 it66353_h2swset(0xF4, 0x80, it66353_gdev.opts.dev_opt->ForceRxOn << 7); in _tx_init()
1700 it66353_h2swset(0x50, 0x0B, 0x08); in _tx_init()
1702 it66353_h2swset(0x3A, 0xC0, (1 << 7) + (0 << 6)); in _tx_init()
1703 it66353_h2swset(0x3B, 0x03, 0); // DDC 75K in _tx_init()
1704 it66353_h2swset(0x43, 0xFC, (0 << 7) + (0 << 5) + (0 << 4) + (2 << 2)); in _tx_init()
1705 it66353_h2swset(0xA9, 0xC0, (it66353_gdev.opts.tx_opt->EnTxChSwap << 7) + in _tx_init()
1710 it66353_h2swset(0x37, 0x78, 0x78); in _tx_init()
1714 it66353_h2swset(0xBD, 0x01, it66353_gdev.opts.tx_opt->EnTxVCLKInv); in _tx_init()
1715 it66353_h2swset(0xA9, 0x20, it66353_gdev.opts.tx_opt->EnTxOutD1t << 5); in _tx_init()
1717 it66353_h2swset(0x50, 0x03, it66353_gdev.vars.Rx_active_port); in _tx_init()
1725 it66353_h2swset(0x09, 0x01, 0x01); // RegSoftTxVRst=1 in _tx_reset()
1726 it66353_h2swset(0x09, 0x01, 0x00); // RegSoftTxVRst=0 in _tx_reset()
1729 it66353_h2swset(0x3B, 0x10, 0x10); // DDC Master Reset in _tx_reset()
1730 it66353_h2swset(0x3B, 0x10, 0x00); in _tx_reset()
1742 it66353_h2swset(0x44, 0x08, 0x00); in _rx_init()
1754 it66353_h2swset(0x44, 0x08, 0x08); in it66353_rx_reset()
1769 it66353_h2swset(0x44, 0x03, RCLKFreqSel); in _sw_init()
1798 it66353_h2swset(0x44, 0x40, 0x00); // EnRxPort2Pwd=0 in _sw_init()
1804 it66353_h2swset(0x11, 0x07, 0x03); in _sw_init()
1807 it66353_h2swset(0x37, 0xE0, 0xE0); in _sw_init()
1808 it66353_h2swset(0x38, 0xF9, 0xF9); in _sw_init()
1811 it66353_h2swset(0x15, 0x08, 0 << 3); in _sw_init()
1813 it66353_h2swset(0x2B, 0x02, 0x00); in _sw_init()
1814 it66353_h2swset(0x2C, 0xC0, 0xC0); in _sw_init()
1816 it66353_h2swset(0x50, 0xf0, 0x00); in _sw_init()
1818 it66353_h2swset(0xC4, 0x08, 0x08); in _sw_init()
1819 it66353_h2swset(0xC5, 0x08, 0x08); in _sw_init()
1820 it66353_h2swset(0xC6, 0x08, 0x08); in _sw_init()
1835 it66353_h2swset(0xF5, 0xE0, in _sw_init()
1840 it66353_h2swset(0x3C, 0x01, 0x01);// disable DDCRegen by set RegTxMastersel=1 in _sw_init()
1841 it66353_h2swset(0xb3, 0x20, 0x20); in _sw_init()
1860 it66353_h2swset(0x4c, 0x40, 0x00); in _sw_init()
1861 it66353_h2swset(0x4d, 0x40, 0x00); in _sw_init()
1862 it66353_h2swset(0x4e, 0x40, 0x00); in _sw_init()
1866 it66353_h2swset(0xB2, 0x60, 0x00); in _sw_init()
1870 it66353_h2swset(0xAC, 0x11, 0x11); in _sw_init()
1882 it66353_h2swset(0x0A, 0x01, 0x01); // SoftRstAll=1 in _sw_reset()
1884 it66353_h2swset(0x44, 0xA0, 0x80);// ForceWrUpd = 1 and SWGateRCLK = 0 in _sw_reset()
1903 it66353_h2swset(0x11, 0x80, 0x80); in it66353_cal_rclk()
1905 it66353_h2swset(0x11, 0x80, 0x00); in it66353_cal_rclk()
1928 it66353_h2swset(0x2C, 0x3F, (u8)wclk_high_num & 0xFF); in it66353_cal_rclk()
1958 it66353_h2swset(0x2c, 0x3f, 0x1a); in it66353_init_rclk()
1968 it66353_h2swset(0x2c, 0x3f, 0x19); in it66353_init_rclk()
1978 it66353_h2swset(0x2c, 0x3f, 0x18); in it66353_init_rclk()
2003 it66353_h2swset(0x50, 0x08, (enable << 3)); in it66353_enable_tx_port()
2024 it66353_h2swset(0xD4, 0x03, 0x01); // Set DRV_RST='0' in it66353_txoe()
2025 it66353_h2swset(0xD4, 0x03, 0x00); // Set DRV_RST='0' in it66353_txoe()
2031 it66353_h2swset(0xD4, 0x07, 0x03); // Set DRV_RST='1' in it66353_txoe()
2042 it66353_h2swset(0xEB, 0x07, 0x02); // output when data ready in it66353_auto_txoe()
2045 it66353_h2swset(0xEA, 0xA2, 0x00); in it66353_auto_txoe()
2046 it66353_h2swset(0xEB, 0x10, 0x00); //[4]RegEnTxDODeskew_doneDly in it66353_auto_txoe()
2048 it66353_h2swset(0xEB, 0x03, 0x01); in it66353_auto_txoe()
2060 it66353_h2swset(0xF4, 0x0C, 0x0C); // TXPWR5V=1 in it66353_set_tx_5v()
2062 it66353_h2swset(0xF4, 0x0C, 0x08); // TXPWR5V=0 in it66353_set_tx_5v()
2551 it66353_h2swset(0x3C, 0x01, 0x01); in it66353_tx_irq()
2569 it66353_h2swset(0x3C, 0x01, 0x01); in it66353_tx_irq()
2580 it66353_h2swset(0x3C, 0x01, 0x01); in it66353_tx_irq()
2692 it66353_h2swset(0x50, 0x03, it66353_gdev.vars.Rx_active_port); in __it66353_fsm_chg()
2774 it66353_h2swset(0x2b, 0x02, 0x00); in __it66353_fsm_chg()
2777 it66353_h2swset(0x2b, 0x02, 0x02); in __it66353_fsm_chg()
2907 it66353_h2swset(0xB2, 0x0A, 0x0A); // W1C AutoH2Mode and AutoScrbEn in __it66353_fsm_chg()
2922 it66353_h2swset(0xB2, 0x0A, 0x0A); // W1C AutoH2Mode and AutoScrbEn in __it66353_fsm_chg()
2957 it66353_h2swset(0x06+it66353_gdev.vars.Rx_active_port, 0x01, 0x01); in _rx_pll_reset()
2959 it66353_h2swset(0x06+it66353_gdev.vars.Rx_active_port, 0x01, 0x00); in _rx_pll_reset()
3609 it66353_h2swset(0x3C, 0x01, 0x01); // Enable PC DDC Mode in it66353_read_edid()
3610 it66353_h2swset(0x38, 0x08, 0x08); // Enable DDC Command Fail Interrupt in it66353_read_edid()
3611 it66353_h2swset(0x37, 0x80, 0x80); // Enable DDC Bus Hang Interrupt in it66353_read_edid()
3801 it66353_h2swset(0xd9 + wcount * 2 + i / 2, in it66353_setup_edid_ram_step2()
3858 it66353_h2swset(0x3C, 0x01, 0x01); in it66353_ddc_abort()
4213 it66353_h2swset(0xF5, 0x80, (1 << 7)); in it66353_write_edid()
4214 it66353_h2swset(0x3C, 0x01, 0x01); // disable DDCRegen by set RegTxMastersel=1 in it66353_write_edid()
4216 it66353_h2swset(0x3C, 0x01, 0x01); // Enable PC DDC Mode in it66353_write_edid()
4217 it66353_h2swset(0x38, 0x08, 0x08); // Enable DDC Command Fail Interrupt in it66353_write_edid()
4218 it66353_h2swset(0x37, 0x80, 0x80); // Enable DDC Bus Hang Interrupt in it66353_write_edid()
4242 it66353_h2swset(0xF5, 0x80, (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass << 7)); in it66353_write_edid()
4245 it66353_h2swset(0x3C, 0x01, 0x00); in it66353_write_edid()