507 u8 it66353_h2rxset(u8 offset, u8 mask, u8 wdata)  in it66353_h2rxset()  function
570 	it66353_h2rxset(0x0f, 0x07, bankno & 0x07);  in it66353_chgrxbank()
1106 	it66353_h2rxset(0x3A, 0x80, 0x00);		// Reg_CAOFTrg low  in it66353_rx_caof_init()
1107 	it66353_h2rxset(0xA0, 0x80, 0x80);  in it66353_rx_caof_init()
1108 	it66353_h2rxset(0xA1, 0x80, 0x80);  in it66353_rx_caof_init()
1109 	it66353_h2rxset(0xA2, 0x80, 0x80);  in it66353_rx_caof_init()
1112 	it66353_h2rxset(0x2A, 0x41, 0x41);		// CAOF RST and CAOFCLK inversion  in it66353_rx_caof_init()
1114 	it66353_h2rxset(0x2A, 0x40, 0x00);		// deassert CAOF RST  in it66353_rx_caof_init()
1116 	it66353_h2rxset(0x3C, 0x10, 0x00);		// disable PLLBufRst  in it66353_rx_caof_init()
1119 	it66353_h2rxset(0x3B, 0xC0, 0x00);		// Reg_ENSOF, Reg_ENCAOF  in it66353_rx_caof_init()
1120 	it66353_h2rxset(0x48, 0x80, 0x80);		// for read back sof value registers  in it66353_rx_caof_init()
1122 	it66353_h2rxset(0x3A, 0x80, 0x80);		// Reg_CAOFTrg high  in it66353_rx_caof_init()
1138 				it66353_h2rxset(0x3A, 0x80, 0x00);// disable CAOF_Trig  in it66353_rx_caof_init()
1140 				it66353_h2rxset(0x2A, 0x40, 0x40);// reset CAOF when caof fail  in it66353_rx_caof_init()
1141 				it66353_h2rxset(0x2A, 0x40, 0x00);  in it66353_rx_caof_init()
1151 	it66353_h2rxset(0x48, 0x80, 0x80);  in it66353_rx_caof_init()
1162 	it66353_h2rxset(0x08, 0x30, 0x30);  in it66353_rx_caof_init()
1163 	it66353_h2rxset(0x3C, 0x10, 0x10);  in it66353_rx_caof_init()
1166 	it66353_h2rxset(0x3A, 0x80, 0x00);	// Reg_CAOFTrg low  in it66353_rx_caof_init()
1167 	it66353_h2rxset(0xA0, 0x80, 0x00);  in it66353_rx_caof_init()
1168 	it66353_h2rxset(0xA1, 0x80, 0x00);  in it66353_rx_caof_init()
1169 	it66353_h2rxset(0xA2, 0x80, 0x00);  in it66353_rx_caof_init()
1198 		it66353_h2rxset(0xA7, 0x40, 0x40);  in _rx_setup_afe()
1200 		it66353_h2rxset(0xA7, 0x40, 0x00);  in _rx_setup_afe()
1288 	it66353_h2rxset(0x60, 0x20, 0x20);	// RegEnIntOut=1  in _rx_int_enable()
1738 	it66353_h2rxset(0x34, 0x01, 0x01);	// Reg_AutoRCLK=1 (default)  in _rx_init()
1739 	it66353_h2rxset(0x21, 0x40, 0x40);	// Reg_AutoEDIDRst=1  in _rx_init()
1741 	it66353_h2rxset(0x3B, 0x20, 0x20);	// CED_Opt  in _rx_init()
1743 	it66353_h2rxset(0x29, 0x40, 0x00);  in _rx_init()
1744 	it66353_h2rxset(0x3C, 0x01, 0x00);  in _rx_init()
1753 	it66353_h2rxset(0x29, 0x40, 0x00);  in it66353_rx_reset()
2762 				it66353_h2rxset(0x3B, 0x10, 0x00);  in __it66353_fsm_chg()
2768 				it66353_h2rxset(0x3B, 0x10, 0x10);  in __it66353_fsm_chg()
3771 		it66353_h2rxset(0x4C, 0x0F, 0x0F);  in it66353_setup_edid_ram_step2()
3839 				it66353_h2rxset(0x4C, 0x0F, mask);  in it66353_setup_edid_ram_step2()
4190 	it66353_h2rxset(0x4C, 0x30, 0x00);  in it66353_dump_register_all()
4192 	it66353_h2rxset(0x4C, 0x30, 0x10);  in it66353_dump_register_all()
4194 	it66353_h2rxset(0x4C, 0x30, 0x20);  in it66353_dump_register_all()
4409 	it66353_h2rxset(0x4C, 0x0F, target_port);  in it66353_set_internal_EDID()
4442 	it66353_h2rxset(0x4C, 0x30, target_port << 4);  in it66353_get_internal_EDID()