Lines Matching refs:it66353_gdev
96 IT6635_DEVICE_DATA it66353_gdev; variable
196 i2c_rd8(it66353_gdev.opts.dev_opt->RxAddr, offset, &rd_data); in rx_rd8()
205 i2c_rd8(it66353_gdev.opts.dev_opt->CecAddr, offset, &rd_data); in cec_rd8()
214 i2c_rd8(it66353_gdev.opts.dev_opt->SwAddr, offset, &rd_data); in sw_rd8()
222 i2c_rd8(it66353_gdev.opts.dev_opt->SwAddr, reg, &val_p); in swAddr_updata_bit()
224 i2c_wr8(it66353_gdev.opts.dev_opt->SwAddr, reg, val_p); in swAddr_updata_bit()
231 i2c_rd8(it66353_gdev.opts.dev_opt->RxAddr, reg, &val_p); in rxAddr_updata_bit()
233 i2c_wr8(it66353_gdev.opts.dev_opt->RxAddr, reg, val_p); in rxAddr_updata_bit()
240 i2c_rd8(it66353_gdev.opts.dev_opt->CecAddr, reg, &val_p); in cecAddr_updata_bit()
242 i2c_wr8(it66353_gdev.opts.dev_opt->CecAddr, reg, val_p); in cecAddr_updata_bit()
622 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass) { in _tx_scdc_write()
656 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass) { in _tx_scdc_read()
691 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass) { in _tx_hdcp_write()
722 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass) { in _tx_hdcp_read()
794 if (it66353_gdev.opts.dev_opt->DoTxPowerDown) { in _tx_power_down()
969 if (it66353_gdev.vars.Rev >= 0xC0) { in _sw_show_hdcp_status()
1172 it66353_rx_auto_power_down_enable(port, it66353_gdev.opts.dev_opt->RxAutoPowerDown); in it66353_rx_caof_init()
1184 if (it66353_gdev.vars.RxCEDErrValid & (0x01 << ch)) { in _rx_show_ced_info()
1185 DEBUG("ch_%d CED=0x%04x\r\n", ch, it66353_gdev.vars.RxCEDErr[ch]); in _rx_show_ced_info()
1231 if (it66353_get_port_info0(it66353_gdev.vars.Rx_active_port, in it66353_rx_is_clock_stable()
1245 if (it66353_gdev.vars.Rev >= 0xC0) { in _rx_need_hpd_toggle()
1355 it66353_gdev.vars.RxHPDFlag[port] = hpd_value; in _rx_set_hpd()
1357 if (it66353_gdev.vars.Rx_active_port == port) { in _rx_set_hpd()
1360 if (it66353_gdev.opts.rx_opt[port]->EnRxDDCBypass == 0) { in _rx_set_hpd()
1367 if (it66353_gdev.opts.rx_opt[port]->DisableEdidRam == 0) { in _rx_set_hpd()
1371 if (it66353_gdev.opts.rx_opt[port]->HPDOutputInverse) { in _rx_set_hpd()
1379 if (it66353_gdev.vars.Rx_active_port == port) { in _rx_set_hpd()
1395 if (it66353_gdev.vars.Rx_active_port == port) { in _rx_set_hpd()
1403 if (it66353_gdev.opts.rx_opt[port]->HPDOutputInverse) { in _rx_set_hpd()
1409 if (port == it66353_gdev.vars.Rx_active_port) { in _rx_set_hpd()
1435 if (it66353_gdev.vars.Rx_active_port == i) { in _rx_set_hpd_with_5v_all()
1440 if (it66353_gdev.opts.rx_opt[i]->NonActivePortReplyHPD) { in _rx_set_hpd_with_5v_all()
1466 if (it66353_gdev.opts.active_rx_opt->EnableAutoEQ) { in it66353it66353_rx_handle_output_err()
1467 if (it66353_gdev.vars.try_fixed_EQ) { in it66353it66353_rx_handle_output_err()
1469 it66353_gdev.vars.try_fixed_EQ = 0; in it66353it66353_rx_handle_output_err()
1608 if (it66353_gdev.vars.current_hdmi_mode == HDMI_MODE_20) { in _sw_monitor_and_fix_scdc_write()
1612 } else if (it66353_gdev.vars.current_hdmi_mode == HDMI_MODE_14) { in _sw_monitor_and_fix_scdc_write()
1630 port = it66353_gdev.vars.Rx_active_port; in _sw_sdi_check()
1632 if (it66353_gdev.vars.sdi_stable_count < 8) { in _sw_sdi_check()
1634 it66353_gdev.vars.sdi_stable_count++; in _sw_sdi_check()
1636 it66353_gdev.vars.sdi_stable_count = 0; in _sw_sdi_check()
1640 it66353_gdev.vars.sdi_stable_count = 0; in _sw_sdi_check()
1662 it66353_gdev.vars.check_for_sdi = 0; in _sw_sdi_check()
1667 it66353_gdev.vars.check_for_sdi = 0; in _sw_sdi_check()
1674 if (it66353_gdev.vars.spmon == 2) { in _sw_hdcp_access_enable()
1692 if (it66353_gdev.opts.dev_opt->ForceRxOn) { in _tx_init()
1696 it66353_h2swset(0xF4, 0x80, it66353_gdev.opts.dev_opt->ForceRxOn << 7); in _tx_init()
1705 it66353_h2swset(0xA9, 0xC0, (it66353_gdev.opts.tx_opt->EnTxChSwap << 7) + in _tx_init()
1706 (it66353_gdev.opts.tx_opt->EnTxPNSwap << 6)); in _tx_init()
1714 it66353_h2swset(0xBD, 0x01, it66353_gdev.opts.tx_opt->EnTxVCLKInv); in _tx_init()
1715 it66353_h2swset(0xA9, 0x20, it66353_gdev.opts.tx_opt->EnTxOutD1t << 5); in _tx_init()
1717 it66353_h2swset(0x50, 0x03, it66353_gdev.vars.Rx_active_port); in _tx_init()
1775 it66353_h2swwr(0xEF, it66353_gdev.opts.dev_opt->RxAddr | 0x01); in _sw_init()
1778 if (it66353_gdev.opts.EnCEC) { in _sw_init()
1782 it66353_h2swwr(0xEE, (it66353_gdev.opts.dev_opt->CecAddr | 0x01)); in _sw_init()
1785 cec_timer_unit = it66353_gdev.vars.RCLK / (16*10); in _sw_init()
1791 it66353_h2swwr(0xEE, (it66353_gdev.opts.dev_opt->CecAddr | 0x01)); in _sw_init()
1795 it66353_h2swwr(0xEE, (it66353_gdev.opts.dev_opt->CecAddr & 0xFE)); in _sw_init()
1801 it66353_rx_caof_init(it66353_gdev.vars.Rx_active_port); in _sw_init()
1826 it66353_rx_auto_power_down_enable_all(it66353_gdev.opts.dev_opt->RxAutoPowerDown); in _sw_init()
1836 (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass << 7)+ in _sw_init()
1837 (it66353_gdev.opts.active_rx_opt->EnRxPWR5VBypass << 6)+ in _sw_init()
1838 (it66353_gdev.opts.active_rx_opt->EnRxHPDBypass << 5)); in _sw_init()
1839 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == 1) { in _sw_init()
1849 if (it66353_gdev.opts.rx_opt[port]->DisableEdidRam) { in _sw_init()
1859 if (it66353_gdev.opts.active_rx_opt->EnRxHPDBypass) { in _sw_init()
1881 it66353_h2swwr(0xEF, it66353_gdev.opts.dev_opt->RxAddr | 0x01); in _sw_reset()
1883 if (it66353_h2swrd(0xEF) == (it66353_gdev.opts.dev_opt->RxAddr | 0x01)) { in _sw_reset()
1941 it66353_gdev.vars.RCLK = rclk; in it66353_cal_rclk()
1949 if (it66353_gdev.opts.EnCEC) { in it66353_init_rclk()
1962 it66353_gdev.vars.RCLK = 20000; in it66353_init_rclk()
1972 it66353_gdev.vars.RCLK = 19569; in it66353_init_rclk()
1982 it66353_gdev.vars.RCLK = 18562; in it66353_init_rclk()
2008 if (it66353_gdev.vars.current_txoe == enable) { in it66353_txoe()
2013 DEBUG("TXOE=%d align=%d\r\n", enable, it66353_gdev.opts.active_rx_opt->TxOEAlignment); in it66353_txoe()
2016 if (it66353_gdev.vars.current_hdmi_mode == HDMI_MODE_20) { in it66353_txoe()
2019 } else if (it66353_gdev.vars.current_hdmi_mode == HDMI_MODE_14) { in it66353_txoe()
2034 it66353_gdev.vars.current_txoe = enable; in it66353_txoe()
2039 DEBUG("A_TXOE=%d align=%d\r\n", enable, it66353_gdev.opts.active_rx_opt->TxOEAlignment); in it66353_auto_txoe()
2054 if (it66353_gdev.vars.Tx_current_5v != output_value) { in it66353_set_tx_5v()
2055 it66353_gdev.vars.Tx_current_5v = output_value; in it66353_set_tx_5v()
2080 _rx_wdog_rst(it66353_gdev.vars.Rx_active_port); in it66353_get_rx_vclk()
2102 tmds_clk = it66353_gdev.vars.RCLK * 256 * wdog_clk_div / tmds_clk_speed; in it66353_get_rx_vclk()
2117 tmds_clk = it66353_gdev.vars.RCLK * 256 * wdog_clk_div / tmds_clk_speed; in it66353_get_rx_vclk()
2171 if (it66353_gdev.vars.Rx_active_port != port) { in it66353_detect_port()
2174 if (it66353_gdev.opts.rx_opt[port]->NonActivePortReplyHPD) { in it66353_detect_port()
2244 if (it66353_gdev.vars.Rx_active_port != i) { in it66353_detect_ports()
2272 if (it66353_gdev.opts.active_rx_opt->TryFixedEQFirst) { in it66353_rx_irq()
2273 it66353_gdev.vars.try_fixed_EQ = 1; in it66353_rx_irq()
2288 it66353_gdev.vars.rx_deskew_err++; in it66353_rx_irq()
2289 if (it66353_gdev.vars.rx_deskew_err > 50) { in it66353_rx_irq()
2290 it66353_gdev.vars.rx_deskew_err = 0; in it66353_rx_irq()
2333 it66353_gdev.vars.count_fsm_err++; in it66353_rx_irq()
2334 if (it66353_gdev.vars.count_fsm_err > 20) { in it66353_rx_irq()
2335 if (it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc) { in it66353_rx_irq()
2341 it66353_gdev.vars.count_fsm_err = 0; in it66353_rx_irq()
2344 if (it66353_gdev.vars.count_fsm_err > 0) { in it66353_rx_irq()
2345 it66353_gdev.vars.count_fsm_err--; in it66353_rx_irq()
2408 if (port == it66353_gdev.vars.Rx_active_port) { in it66353_sw_irq()
2411 if (it66353_gdev.vars.RxHPDFlag[it66353_gdev.vars.Rx_active_port] > 0) { in it66353_sw_irq()
2428 if (it66353_gdev.vars.RxHPDFlag[port]) { in it66353_sw_irq()
2432 it66353_gdev.vars.vclk = it66353_get_rx_vclk(it66353_gdev.vars.Rx_active_port); in it66353_sw_irq()
2433 if ((it66353_gdev.vars.vclk != it66353_gdev.vars.vclk_prev)) { in it66353_sw_irq()
2434 it66353_gdev.vars.vclk_prev = it66353_gdev.vars.vclk; in it66353_sw_irq()
2435 if (it66353_gdev.vars.RxHPDFlag[port]) { in it66353_sw_irq()
2453 if (it66353_gdev.vars.Rx_active_port == port) { in it66353_sw_irq()
2455 it66353_auto_txoe(it66353_gdev.opts.active_rx_opt->TxOEAlignment); in it66353_sw_irq()
2461 if (new_ratio != it66353_gdev.vars.clock_ratio) { in it66353_sw_irq()
2478 if (it66353_gdev.vars.Rx_active_port == port) { in it66353_sw_irq()
2479 if (new_scramble != it66353_gdev.vars.h2_scramble) { in it66353_sw_irq()
2526 if (it66353_gdev.vars.state_sys_fsm != RX_TOGGLE_HPD && in it66353_tx_irq()
2527 it66353_gdev.vars.state_sys_fsm != RX_UNPLUG) { in it66353_tx_irq()
2549 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_tx_irq()
2567 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_tx_irq()
2578 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_tx_irq()
2627 if (new_state <= IDLE && it66353_gdev.vars.state_sys_fsm <= IDLE) { in __it66353_fsm_chg()
2629 s__SYS_FSM_STATE[it66353_gdev.vars.state_sys_fsm], in __it66353_fsm_chg()
2633 it66353_gdev.vars.state_sys_fsm, new_state, caller); in __it66353_fsm_chg()
2636 DEBUG("state_fsm %d -> %d\r\n", it66353_gdev.vars.state_sys_fsm, new_state); in __it66353_fsm_chg()
2640 if (it66353_gdev.vars.state_sys_fsm == new_state) { in __it66353_fsm_chg()
2648 if (it66353_gdev.vars.RxHPDFlag[it66353_gdev.vars.Rx_active_port] == 0) { in __it66353_fsm_chg()
2656 it66353_gdev.vars.state_sys_fsm = new_state; in __it66353_fsm_chg()
2657 it66353_gdev.vars.fsm_return = 0; in __it66353_fsm_chg()
2659 switch (it66353_gdev.vars.state_sys_fsm) { in __it66353_fsm_chg()
2661 _sw_enable_hpd_toggle_timer(it66353_gdev.vars.hpd_toggle_timeout); in __it66353_fsm_chg()
2667 it66353_gdev.vars.Rx_active_port, it66353_gdev.vars.Rx_new_port); in __it66353_fsm_chg()
2668 if (it66353_gdev.vars.clock_ratio > 0 && in __it66353_fsm_chg()
2669 it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in __it66353_fsm_chg()
2672 if (it66353_gdev.opts.tx_opt->TurnOffTx5VWhenSwitchPort) { in __it66353_fsm_chg()
2680 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, 0, TERM_FOLLOW_HPD); in __it66353_fsm_chg()
2687 it66353_gdev.vars.force_hpd_state = SW_HPD_AUTO; in __it66353_fsm_chg()
2688 it66353_gdev.vars.Rx_active_port = it66353_gdev.vars.Rx_new_port; in __it66353_fsm_chg()
2692 it66353_h2swset(0x50, 0x03, it66353_gdev.vars.Rx_active_port); in __it66353_fsm_chg()
2694 it66353_set_RS(it66353_gdev.opts.active_rx_opt->DefaultEQ[0], in __it66353_fsm_chg()
2695 it66353_gdev.opts.active_rx_opt->DefaultEQ[1], in __it66353_fsm_chg()
2696 it66353_gdev.opts.active_rx_opt->DefaultEQ[2]); in __it66353_fsm_chg()
2698 it66353_gdev.EQ.sys_aEQ = SysAEQ_RUN; in __it66353_fsm_chg()
2705 it66353_gdev.vars.count_symlock_lost = 0; in __it66353_fsm_chg()
2706 it66353_gdev.vars.count_symlock_unstable = 0; in __it66353_fsm_chg()
2708 if ((it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc) && in __it66353_fsm_chg()
2709 (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == FALSE)) { in __it66353_fsm_chg()
2710 if (it66353_gdev.vars.current_hdmi_mode == HDMI_MODE_20) { in __it66353_fsm_chg()
2712 } else if (it66353_gdev.vars.current_hdmi_mode == HDMI_MODE_14) { in __it66353_fsm_chg()
2722 if (it66353_gdev.vars.spmon == 1) { in __it66353_fsm_chg()
2723 if ((it66353_gdev.opts.active_rx_opt->DisableEdidRam & in __it66353_fsm_chg()
2724 (1 << it66353_gdev.vars.Rx_active_port)) == 0) { in __it66353_fsm_chg()
2725 _rx_edid_ram_enable(it66353_gdev.vars.Rx_active_port); in __it66353_fsm_chg()
2731 it66353_gdev.vars.count_try_force_hdmi_mode = 0; in __it66353_fsm_chg()
2740 it66353_gdev.vars.count_symlock_fail = 0; in __it66353_fsm_chg()
2748 it66353_rx_term_power_down(it66353_gdev.vars.Rx_active_port, 0x00); in __it66353_fsm_chg()
2749 it66353_gdev.vars.vclk = it66353_get_rx_vclk(it66353_gdev.vars.Rx_active_port); in __it66353_fsm_chg()
2751 if (it66353_gdev.vars.vclk) { in __it66353_fsm_chg()
2752 it66353_gdev.vars.clock_ratio = in __it66353_fsm_chg()
2753 ((it66353_h2swrd(0x61 + it66353_gdev.vars.Rx_active_port * 3) >> 6) & 1); in __it66353_fsm_chg()
2755 it66353_gdev.vars.clock_ratio); in __it66353_fsm_chg()
2757 if (it66353_gdev.vars.clock_ratio > 0) { in __it66353_fsm_chg()
2758 if (it66353_gdev.vars.vclk < 300000UL) { in __it66353_fsm_chg()
2759 it66353_gdev.vars.vclk = 300001UL; in __it66353_fsm_chg()
2764 if (it66353_gdev.vars.vclk >= 300000UL) { in __it66353_fsm_chg()
2765 it66353_gdev.vars.vclk = 297000UL; in __it66353_fsm_chg()
2771 if (it66353_gdev.vars.vclk < 35000UL) { in __it66353_fsm_chg()
2782 _rx_setup_afe(it66353_gdev.vars.vclk); in __it66353_fsm_chg()
2783 _tx_setup_afe(it66353_gdev.vars.vclk); in __it66353_fsm_chg()
2785 if (it66353_gdev.vars.clock_ratio == 0) { in __it66353_fsm_chg()
2789 it66353_auto_txoe(it66353_gdev.opts.active_rx_opt->TxOEAlignment); in __it66353_fsm_chg()
2791 it66353_gdev.opts.active_rx_opt->TxOEAlignment); in __it66353_fsm_chg()
2801 if (it66353_gdev.opts.dev_opt->TxPowerDownWhileWaitingClock) { in __it66353_fsm_chg()
2810 it66353_gdev.vars.RxCEDErrRec[1][0] = 0xffff; in __it66353_fsm_chg()
2811 it66353_gdev.vars.RxCEDErrRec[1][1] = 0xffff; in __it66353_fsm_chg()
2812 it66353_gdev.vars.RxCEDErrRec[1][2] = 0xffff; in __it66353_fsm_chg()
2813 it66353_gdev.EQ.manu_eq_fine_tune_count[0] = 0; in __it66353_fsm_chg()
2814 it66353_gdev.EQ.manu_eq_fine_tune_count[1] = 0; in __it66353_fsm_chg()
2815 it66353_gdev.EQ.manu_eq_fine_tune_count[2] = 0; in __it66353_fsm_chg()
2816 it66353_gdev.EQ.ced_err_avg_prev[0] = 0x8888; in __it66353_fsm_chg()
2817 it66353_gdev.EQ.ced_err_avg_prev[1] = 0x8888; in __it66353_fsm_chg()
2818 it66353_gdev.EQ.ced_err_avg_prev[2] = 0x8888; in __it66353_fsm_chg()
2819 it66353_gdev.EQ.ced_acc_count = 0; in __it66353_fsm_chg()
2821 it66353_gdev.vars.count_symlock = 0; in __it66353_fsm_chg()
2822 it66353_gdev.vars.count_unlock = 0; in __it66353_fsm_chg()
2823 it66353_gdev.vars.check_for_hpd_toggle = 0; in __it66353_fsm_chg()
2824 it66353_gdev.vars.sdi_stable_count = 0; in __it66353_fsm_chg()
2825 it66353_gdev.vars.check_for_sdi = 1; in __it66353_fsm_chg()
2826 it66353_gdev.vars.rx_deskew_err = 0; in __it66353_fsm_chg()
2836 it66353it66353_rx_ovwr_hdmi_clk(it66353_gdev.vars.Rx_active_port, RX_CLK_H20); in __it66353_fsm_chg()
2837 it66353it66353_rx_ovwr_h20_scrb(it66353_gdev.vars.Rx_active_port, 1); in __it66353_fsm_chg()
2844 _sw_int_enable(it66353_gdev.vars.Rx_active_port, 1); in __it66353_fsm_chg()
2846 _rx_wdog_rst(it66353_gdev.vars.Rx_active_port); in __it66353_fsm_chg()
2847 if (it66353_gdev.vars.spmon == 1) { in __it66353_fsm_chg()
2848 if ((it66353_gdev.opts.active_rx_opt->DisableEdidRam & in __it66353_fsm_chg()
2849 (1<<it66353_gdev.vars.Rx_active_port)) == 0) { in __it66353_fsm_chg()
2850 _rx_edid_ram_disable(it66353_gdev.vars.Rx_active_port); in __it66353_fsm_chg()
2854 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, 1, TERM_FOLLOW_HPD); in __it66353_fsm_chg()
2855 if (it66353_gdev.vars.is_hdmi20_sink == 0) { in __it66353_fsm_chg()
2858 it66353_auto_txoe(it66353_gdev.opts.active_rx_opt->TxOEAlignment); in __it66353_fsm_chg()
2868 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in __it66353_fsm_chg()
2870 it66353_gdev.vars.edid_ready = 1; in __it66353_fsm_chg()
2874 if (it66353_gdev.opts.EnCEC) { in __it66353_fsm_chg()
2875 u8 u8phyAB = (it66353_gdev.vars.PhyAdr[0] << 4) | (it66353_gdev.vars.PhyAdr[1] & 0xF); in __it66353_fsm_chg()
2876 u8 u8phyCD = (it66353_gdev.vars.PhyAdr[2] << 4) | (it66353_gdev.vars.PhyAdr[3] & 0xF); in __it66353_fsm_chg()
2878 CecSys_Init(u8phyAB, u8phyCD, it66353_gdev.vars.Rx_active_port); in __it66353_fsm_chg()
2882 if (it66353_gdev.opts.active_rx_opt->NonActivePortReplyHPD) { in __it66353_fsm_chg()
2903 it66353_gdev.vars.edid_ready = 0; in __it66353_fsm_chg()
2905 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, 0, TERM_FOLLOW_TX); in __it66353_fsm_chg()
2915 if (it66353_gdev.vars.force_hpd_state == SW_HPD_LOW) { in __it66353_fsm_chg()
2916 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, 0, TERM_FOLLOW_HPD); in __it66353_fsm_chg()
2918 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, 0, TERM_FOLLOW_TX); in __it66353_fsm_chg()
2938 if (new_state <= IDLE && it66353_gdev.vars.state_sys_fsm <= IDLE) { in __it66353_fsm_chg2()
2940 s__SYS_FSM_STATE[it66353_gdev.vars.state_sys_fsm], in __it66353_fsm_chg2()
2944 it66353_gdev.vars.state_sys_fsm, new_state, caller); in __it66353_fsm_chg2()
2948 it66353_gdev.vars.state_sys_fsm, new_state); in __it66353_fsm_chg2()
2952 it66353_gdev.vars.fsm_return = 1; in __it66353_fsm_chg2()
2957 it66353_h2swset(0x06+it66353_gdev.vars.Rx_active_port, 0x01, 0x01); in _rx_pll_reset()
2959 it66353_h2swset(0x06+it66353_gdev.vars.Rx_active_port, 0x01, 0x00); in _rx_pll_reset()
2964 _rx_ovwr_hdmi_mode(it66353_gdev.vars.Rx_active_port, HDMI_MODE_AUTO); in it66353_auto_detect_hdmi_encoding()
2966 it66353_gdev.vars.current_hdmi_mode = HDMI_MODE_AUTO; in it66353_auto_detect_hdmi_encoding()
2973 _rx_ovwr_hdmi_mode(it66353_gdev.vars.Rx_active_port, HDMI_MODE_20); in it66353_force_hdmi20()
2975 it66353_gdev.vars.current_hdmi_mode = HDMI_MODE_20; in it66353_force_hdmi20()
2982 _rx_ovwr_hdmi_mode(it66353_gdev.vars.Rx_active_port, HDMI_MODE_14); in it66353_force_hdmi14()
2984 it66353_gdev.vars.current_hdmi_mode = HDMI_MODE_14; in it66353_force_hdmi14()
2992 switch (it66353_gdev.vars.current_hdmi_mode) { in it66353_fix_incorrect_hdmi_encoding()
3036 it66353_gdev.vars.check_for_hpd_toggle = 1; in it66353_fsm_EQ_check()
3044 it66353_gdev.vars.check_for_hpd_toggle = 1; in it66353_fsm_EQ_check()
3076 switch (it66353_gdev.vars.state_sys_fsm) { in it66353_fsm()
3078 if ((it66353_gdev.opts.active_rx_opt->NonActivePortReplyHPD == 0) && in it66353_fsm()
3079 (it66353_gdev.opts.tx_opt->TurnOffTx5VWhenSwitchPort == 0)) { in it66353_fsm()
3092 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, 0, TERM_FOLLOW_HPD); in it66353_fsm()
3094 it66353_rx_caof_init(it66353_gdev.vars.Rx_active_port); in it66353_fsm()
3096 it66353_gdev.vars.hpd_toggle_timeout = it66353_gdev.opts.active_rx_opt->HPDTogglePeriod; in it66353_fsm()
3105 it66353_gdev.vars.count_symlock_lost++; in it66353_fsm()
3108 it66353_gdev.vars.count_symlock_lost); in it66353_fsm()
3109 if (it66353_gdev.vars.count_symlock_lost == 100) { in it66353_fsm()
3117 it66353_gdev.vars.count_symlock_unstable++; in it66353_fsm()
3120 it66353_gdev.vars.count_symlock_unstable); in it66353_fsm()
3121 if (it66353_gdev.vars.count_symlock_unstable > 8) { in it66353_fsm()
3128 it66353_gdev.vars.count_symlock_lost = 0; in it66353_fsm()
3129 it66353_gdev.vars.count_symlock_unstable = 0; in it66353_fsm()
3139 if (it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc) { in it66353_fsm()
3144 if (it66353_gdev.vars.current_hdmi_mode != in it66353_fsm()
3145 HDMI_MODE_AUTO && it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == in it66353_fsm()
3151 if (it66353_gdev.vars.check_for_sdi) { in it66353_fsm()
3166 it66353_gdev.vars.count_symlock_fail++; in it66353_fsm()
3167 if (it66353_gdev.vars.count_symlock_fail > 3) { in it66353_fsm()
3168 it66353_gdev.vars.count_symlock_fail = 0; in it66353_fsm()
3171 if (it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc) { in it66353_fsm()
3172 if (it66353_gdev.vars.count_try_force_hdmi_mode < 6) { in it66353_fsm()
3173 it66353_gdev.vars.count_try_force_hdmi_mode++; in it66353_fsm()
3176 it66353_gdev.vars.count_try_force_hdmi_mode = 0; in it66353_fsm()
3188 if ((it66353_gdev.vars.check_for_hpd_toggle == 1) && in it66353_fsm()
3189 (it66353_gdev.vars.current_txoe == 0) && in it66353_fsm()
3193 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, 0, TERM_FOLLOW_HPD); in it66353_fsm()
3243 if (it66353_gdev.vars.vclk == 0) { in it66353_fsm()
3247 if (it66353_gdev.vars.try_fixed_EQ) { in it66353_fsm()
3252 if (it66353_gdev.opts.active_rx_opt->EnableAutoEQ) { in it66353_fsm()
3277 if (it66353_gdev.vars.RxHPDFlag[it66353_gdev.vars.Rx_active_port] == 0) { in it66353_fsm()
3281 if (it66353_gdev.vars.current_hdmi_mode != HDMI_MODE_AUTO) { in it66353_fsm()
3282 it66353_gdev.vars.count_wait_clock++; in it66353_fsm()
3283 if (it66353_gdev.vars.count_wait_clock > 100) { in it66353_fsm()
3284 it66353_gdev.vars.count_wait_clock = 0; in it66353_fsm()
3320 if (it66353_gdev.vars.force_hpd_state == SW_HPD_LOW) { in it66353_fsm()
3324 if (it66353_gdev.vars.state_sys_fsm != RX_TOGGLE_HPD) { in it66353_fsm()
3338 if (it66353_gdev.vars.fsm_return == 0) { in it66353_fsm()
3339 it66353_gdev.vars.fsm_return = 1; in it66353_fsm()
3352 if (it66353_gdev.vars.state_sys_fsm == RX_TOGGLE_HPD) { in it66353_irq()
3389 it66353_sw_irq(it66353_gdev.vars.Rx_active_port); in it66353_irq()
3394 if (it66353_gdev.opts.EnCEC && (sys_int_sts & 0x80)) { in it66353_irq()
3397 if (it66353_gdev.opts.EnCEC) { in it66353_irq()
3409 switch (it66353_gdev.vars.state_dev_init) { in it66353_device_init()
3427 it66353_set_RS(it66353_gdev.opts.active_rx_opt->DefaultEQ[0], in it66353_device_init()
3428 it66353_gdev.opts.active_rx_opt->DefaultEQ[1], in it66353_device_init()
3429 it66353_gdev.opts.active_rx_opt->DefaultEQ[2]); in it66353_device_init()
3430 if (it66353_gdev.opts.tx_opt->CopyEDIDFromSink) { in it66353_device_init()
3432 it66353_gdev.vars.state_dev_init = 1; in it66353_device_init()
3433 it66353_gdev.vars.hpd_wait_count = 0; in it66353_device_init()
3435 it66353_gdev.vars.state_dev_init = 2; in it66353_device_init()
3441 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_device_init()
3443 it66353_gdev.vars.edid_ready = 1; in it66353_device_init()
3445 it66353_gdev.vars.state_dev_init = 3; in it66353_device_init()
3447 it66353_gdev.vars.edid_ready = 1; in it66353_device_init()
3448 it66353_gdev.vars.state_dev_init = 3; in it66353_device_init()
3451 it66353_gdev.vars.hpd_wait_count++; in it66353_device_init()
3452 if (it66353_gdev.vars.hpd_wait_count > 200) { in it66353_device_init()
3454 it66353_gdev.vars.hpd_wait_count = 0; in it66353_device_init()
3464 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_device_init()
3465 it66353_gdev.vars.default_edid[0] = it66353_s_default_edid_port0; in it66353_device_init()
3466 it66353_gdev.vars.default_edid[1] = it66353_s_default_edid_port0; in it66353_device_init()
3467 it66353_gdev.vars.default_edid[2] = it66353_s_default_edid_port0; in it66353_device_init()
3468 it66353_gdev.vars.default_edid[3] = it66353_s_default_edid_port0; in it66353_device_init()
3485 it66353_gdev.vars.edid_ready = 1; in it66353_device_init()
3486 it66353_gdev.vars.state_dev_init = 3; in it66353_device_init()
3495 it66353_gdev.vars.Rx_active_port); in it66353_device_init()
3503 it66353_gdev.vars.state_dev_init = 0; in it66353_device_init()
3513 it66353_gdev.vars.state_dev_init = 0; in it66353_vars_init()
3514 it66353_gdev.vars.VSDBOffset = 0xFF; in it66353_vars_init()
3515 it66353_gdev.vars.PhyAdr[0] = 0; in it66353_vars_init()
3516 it66353_gdev.vars.PhyAdr[1] = 0; in it66353_vars_init()
3517 it66353_gdev.vars.PhyAdr[2] = 0; in it66353_vars_init()
3518 it66353_gdev.vars.PhyAdr[3] = 0; in it66353_vars_init()
3519 it66353_gdev.vars.RxHPDFlag[0] = -1; in it66353_vars_init()
3520 it66353_gdev.vars.RxHPDFlag[1] = -1; in it66353_vars_init()
3521 it66353_gdev.vars.RxHPDFlag[2] = -1; in it66353_vars_init()
3522 it66353_gdev.vars.RxHPDFlag[3] = -1; in it66353_vars_init()
3523 it66353_gdev.vars.Tx_current_5v = -1; in it66353_vars_init()
3524 it66353_gdev.vars.count_eq_check = 0; in it66353_vars_init()
3525 it66353_gdev.vars.count_fsm_err = 0; in it66353_vars_init()
3526 it66353_gdev.vars.count_unlock = 0; in it66353_vars_init()
3527 it66353_gdev.vars.state_sys_fsm = RX_UNPLUG; in it66353_vars_init()
3528 it66353_gdev.EQ.AutoEQ_state = AEQ_OFF; in it66353_vars_init()
3529 it66353_gdev.EQ.sys_aEQ = SysAEQ_RUN; in it66353_vars_init()
3530 it66353_gdev.vars.edid_ready = 0; in it66353_vars_init()
3531 it66353_gdev.vars.current_txoe = 0xFF; in it66353_vars_init()
3532 it66353_gdev.vars.check_for_hpd_toggle = 0; in it66353_vars_init()
3533 it66353_gdev.vars.sdi_stable_count = 0; in it66353_vars_init()
3534 it66353_gdev.vars.check_for_sdi = 1; in it66353_vars_init()
3535 it66353_gdev.vars.force_hpd_state = SW_HPD_AUTO; // 1 : auto, don't modify here in it66353_vars_init()
3536 it66353_gdev.vars.vclk_prev = 0; in it66353_vars_init()
3537 if (it66353_gdev.opts.active_rx_opt->TryFixedEQFirst) { in it66353_vars_init()
3538 it66353_gdev.vars.try_fixed_EQ = 1; in it66353_vars_init()
3540 it66353_gdev.vars.current_hdmi_mode = HDMI_MODE_AUTO; in it66353_vars_init()
3541 it66353_gdev.vars.rx_deskew_err = 0; in it66353_vars_init()
3575 it66353_gdev.vars.Rev = it66353_h2swrd(0x04); in it66353_is_device_ready()
3577 (int)it66353_gdev.vars.Rev); in it66353_is_device_ready()
3583 it66353_gdev.vars.Rev = it66353_h2swrd(0x05); in it66353_is_device_ready()
3585 (int)it66353_gdev.vars.Rev); in it66353_is_device_ready()
3693 it66353_gdev.vars.is_hdmi20_sink = 1; in it66353_parse_edid_for_vsdb()
3704 dev_info(g_it66353->dev, "HDMI2 sink=%d\n", it66353_gdev.vars.is_hdmi20_sink); in it66353_parse_edid_for_vsdb()
3733 it66353_gdev.vars.VSDBOffset = ((u8)off) + 0x80 + 4; in it66353_parse_edid_for_phyaddr()
3734 it66353_gdev.vars.PhyAdr[0] = (edid[off + 4] >> 4) & 0xF; in it66353_parse_edid_for_phyaddr()
3735 it66353_gdev.vars.PhyAdr[1] = edid[off + 4] & 0xF; in it66353_parse_edid_for_phyaddr()
3736 it66353_gdev.vars.PhyAdr[2] = (edid[off + 5] >> 4) & 0xF; in it66353_parse_edid_for_phyaddr()
3737 it66353_gdev.vars.PhyAdr[3] = edid[off + 5] & 0xF; in it66353_parse_edid_for_phyaddr()
3738 it66353_gdev.vars.EdidChkSum[1] = in it66353_parse_edid_for_phyaddr()
3765 _rx_edid_set_chksum(i, it66353_gdev.vars.EdidChkSum[0]); in it66353_setup_edid_ram_step2()
3770 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr | 0x01); in it66353_setup_edid_ram_step2()
3773 it66353_h2swwr(0xe9, it66353_gdev.vars.VSDBOffset); // VSDB_Offset in it66353_setup_edid_ram_step2()
3774 dev_info(g_it66353->dev, "VSDB=%02x\r\n", it66353_gdev.vars.VSDBOffset); in it66353_setup_edid_ram_step2()
3777 if (it66353_gdev.vars.PhyAdr[0] && it66353_gdev.vars.PhyAdr[1] && in it66353_setup_edid_ram_step2()
3778 it66353_gdev.vars.PhyAdr[2] && it66353_gdev.vars.PhyAdr[3]) { in it66353_setup_edid_ram_step2()
3779 it66353_gdev.vars.PhyAdr[0] = 0xF; in it66353_setup_edid_ram_step2()
3780 it66353_gdev.vars.PhyAdr[1] = 0xF; in it66353_setup_edid_ram_step2()
3781 it66353_gdev.vars.PhyAdr[2] = 0xF; in it66353_setup_edid_ram_step2()
3782 it66353_gdev.vars.PhyAdr[3] = 0xF; in it66353_setup_edid_ram_step2()
3785 phyAB = (it66353_gdev.vars.PhyAdr[0] << 4) | (it66353_gdev.vars.PhyAdr[1] & 0xF); in it66353_setup_edid_ram_step2()
3786 phyCD = (it66353_gdev.vars.PhyAdr[2] << 4) | (it66353_gdev.vars.PhyAdr[3] & 0xF); in it66353_setup_edid_ram_step2()
3794 if (it66353_gdev.vars.PhyAdr[i] == 0) { in it66353_setup_edid_ram_step2()
3813 sum = (0x100 - it66353_gdev.vars.EdidChkSum[1] - phyAB - phyCD) & 0xFF; in it66353_setup_edid_ram_step2()
3841 it66353_h2rxedidwr(it66353_gdev.vars.VSDBOffset, &phyAB, 1); in it66353_setup_edid_ram_step2()
3842 it66353_h2rxedidwr(it66353_gdev.vars.VSDBOffset + 1, &phyCD, 1); in it66353_setup_edid_ram_step2()
3849 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr); in it66353_setup_edid_ram_step2()
3887 if (it66353_gdev.opts.tx_opt->CopyEDIDFromSink) { in it66353_update_edid()
3898 u8 *def_edid = it66353_gdev.vars.default_edid[flag]; in it66353_update_edid()
3919 it66353_gdev.vars.spmon = 0; in it66353_setup_edid_ram()
3920 it66353_gdev.vars.is_hdmi20_sink = 0; in it66353_setup_edid_ram()
3930 it66353_gdev.vars.spmon = 1; in it66353_setup_edid_ram()
3938 it66353_gdev.vars.spmon = 2; in it66353_setup_edid_ram()
3949 it66353_gdev.vars.spmon = 3; in it66353_setup_edid_ram()
3954 it66353_gdev.vars.EdidChkSum[0] = edid_tmp[0x7F]; in it66353_setup_edid_ram()
3959 it66353_gdev.vars.EdidChkSum[0] = _rx_calc_edid_sum(edid_tmp); in it66353_setup_edid_ram()
3965 if (it66353_gdev.opts.tx_opt->CopyEDIDFromSink) { in it66353_setup_edid_ram()
3984 it66353_gdev.vars.VSDBOffset = 0; in it66353_setup_edid_ram()
3988 if (it66353_gdev.vars.spmon == 2) { in it66353_setup_edid_ram()
3990 it66353_gdev.vars.spmon = 0; in it66353_setup_edid_ram()
3996 if (it66353_gdev.opts.tx_opt->CopyEDIDFromSink) { in it66353_setup_edid_ram()
4004 if (it66353_gdev.opts.tx_opt->ParsePhysicalAddr) { in it66353_setup_edid_ram()
4007 if (it66353_gdev.vars.VSDBOffset) { in it66353_setup_edid_ram()
4067 it66353_gdev.opts.active_rx_opt->tag1); in it66353_dump_opts()
4069 it66353_gdev.opts.active_rx_opt->EnRxDDCBypass); in it66353_dump_opts()
4071 it66353_gdev.opts.active_rx_opt->EnRxPWR5VBypass); in it66353_dump_opts()
4073 it66353_gdev.opts.active_rx_opt->EnRxHPDBypass); in it66353_dump_opts()
4075 it66353_gdev.opts.active_rx_opt->TryFixedEQFirst); in it66353_dump_opts()
4077 it66353_gdev.opts.active_rx_opt->EnableAutoEQ); in it66353_dump_opts()
4079 it66353_gdev.opts.active_rx_opt->NonActivePortReplyHPD); in it66353_dump_opts()
4081 it66353_gdev.opts.active_rx_opt->DisableEdidRam); in it66353_dump_opts()
4083 it66353_gdev.opts.active_rx_opt->DefaultEQ[0], in it66353_dump_opts()
4084 it66353_gdev.opts.active_rx_opt->DefaultEQ[1], in it66353_dump_opts()
4085 it66353_gdev.opts.active_rx_opt->DefaultEQ[2]); in it66353_dump_opts()
4087 it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc); in it66353_dump_opts()
4089 it66353_gdev.opts.active_rx_opt->HPDOutputInverse); in it66353_dump_opts()
4091 it66353_gdev.opts.active_rx_opt->HPDTogglePeriod); in it66353_dump_opts()
4093 it66353_gdev.opts.active_rx_opt->TxOEAlignment); in it66353_dump_opts()
4095 it66353_gdev.opts.active_rx_opt->str_size); in it66353_dump_opts()
4097 dev_info(g_it66353->dev, ".tx_opt->tag1=%d\r\n", it66353_gdev.opts.tx_opt->tag1); in it66353_dump_opts()
4099 it66353_gdev.opts.tx_opt->EnTxPNSwap); in it66353_dump_opts()
4101 it66353_gdev.opts.tx_opt->EnTxChSwap); in it66353_dump_opts()
4103 it66353_gdev.opts.tx_opt->EnTxVCLKInv); in it66353_dump_opts()
4105 it66353_gdev.opts.tx_opt->EnTxOutD1t); in it66353_dump_opts()
4107 it66353_gdev.opts.tx_opt->CopyEDIDFromSink); in it66353_dump_opts()
4109 it66353_gdev.opts.tx_opt->ParsePhysicalAddr); in it66353_dump_opts()
4111 it66353_gdev.opts.tx_opt->TurnOffTx5VWhenSwitchPort); in it66353_dump_opts()
4113 it66353_gdev.opts.tx_opt->str_size); in it66353_dump_opts()
4116 it66353_gdev.opts.dev_opt->tag1); in it66353_dump_opts()
4118 it66353_gdev.opts.dev_opt->SwAddr); in it66353_dump_opts()
4120 it66353_gdev.opts.dev_opt->RxAddr); in it66353_dump_opts()
4122 it66353_gdev.opts.dev_opt->CecAddr); in it66353_dump_opts()
4124 it66353_gdev.opts.dev_opt->EdidAddr); in it66353_dump_opts()
4126 it66353_gdev.opts.dev_opt->ForceRxOn); in it66353_dump_opts()
4128 it66353_gdev.opts.dev_opt->RxAutoPowerDown); in it66353_dump_opts()
4130 it66353_gdev.opts.dev_opt->DoTxPowerDown); in it66353_dump_opts()
4132 it66353_gdev.opts.dev_opt->TxPowerDownWhileWaitingClock); in it66353_dump_opts()
4134 it66353_gdev.opts.dev_opt->str_size); in it66353_dump_opts()
4179 it66353_dump_register(it66353_gdev.opts.dev_opt->SwAddr, "\n*** Switch Register:\n"); in it66353_dump_register_all()
4181 it66353_dump_register(it66353_gdev.opts.dev_opt->RxAddr, "\n*** RX Register(0):\n"); in it66353_dump_register_all()
4183 it66353_dump_register(it66353_gdev.opts.dev_opt->RxAddr, "\n*** RX Register(3):\n"); in it66353_dump_register_all()
4185 it66353_dump_register(it66353_gdev.opts.dev_opt->RxAddr, "\n*** RX Register(5):\n"); in it66353_dump_register_all()
4189 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr | 0x01); in it66353_dump_register_all()
4191 it66353_dump_register(it66353_gdev.opts.dev_opt->EdidAddr, "\n*** EDID Port 0:\n"); in it66353_dump_register_all()
4193 it66353_dump_register(it66353_gdev.opts.dev_opt->EdidAddr, "\n*** EDID Port 1:\n"); in it66353_dump_register_all()
4195 it66353_dump_register(it66353_gdev.opts.dev_opt->EdidAddr, "\n*** EDID Port 2:\n"); in it66353_dump_register_all()
4196 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr); // disable EDID RAM i2c address in it66353_dump_register_all()
4199 it66353_dump_register(it66353_gdev.opts.dev_opt->CecAddr, "\n*** CEC Register:\n"); in it66353_dump_register_all()
4242 it66353_h2swset(0xF5, 0x80, (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass << 7)); in it66353_write_edid()
4243 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == 0) { in it66353_write_edid()
4304 if (it66353_gdev.vars.Rx_active_port != port) { in it66353_set_active_port()
4305 it66353_gdev.vars.Rx_new_port = port; in it66353_set_active_port()
4319 return it66353_gdev.vars.Rx_active_port; in it66353_get_active_port()
4341 it66353_gdev.vars.state_sys_fsm = RX_UNPLUG; in it66353_dev_restart()
4382 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, hpd_value, TERM_FOLLOW_HPD); in it66353_set_rx_hpd()
4407 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr | 0x01); in it66353_set_internal_EDID()
4416 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr); in it66353_set_internal_EDID()
4441 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr | 0x01); in it66353_get_internal_EDID()
4449 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr); in it66353_get_internal_EDID()
4470 it66353_gdev.opts.rx_opt[port]->DefaultEQ[0] = new_rs_idx0; in it66353_change_default_RS()
4471 it66353_gdev.opts.rx_opt[port]->DefaultEQ[1] = new_rs_idx1; in it66353_change_default_RS()
4472 it66353_gdev.opts.rx_opt[port]->DefaultEQ[2] = new_rs_idx2; in it66353_change_default_RS()
4473 if (update_hw && (port == it66353_gdev.vars.Rx_active_port)) { in it66353_change_default_RS()
4496 it66353_gdev.vars.force_hpd_state = hpd_state; in it66353_force_rx_hpd()
4502 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, hpd_state, TERM_FOLLOW_HPD); in it66353_force_rx_hpd()
4530 _rx_set_hpd(it66353_gdev.vars.Rx_active_port, 0, TERM_FOLLOW_HPD); in it66353_toggle_hpd()
4532 it66353_gdev.vars.hpd_toggle_timeout = timeout; in it66353_toggle_hpd()