Lines Matching +full:chg +full:- +full:status
1 // SPDX-License-Identifier: GPL-2.0
8 * Wangqiang Guo<kay.guo@rock-chips.com>
28 #include <linux/i2c-dev.h>
58 #define PR_IO(x) { if (g_enable_io_log) dev_dbg(g_it66353->dev, x); }
107 struct i2c_client *client = it66353->client; in i2c_wr()
113 msg.addr = client->addr; in i2c_wr()
117 err = i2c_transfer(client->adapter, &msg, 1); in i2c_wr()
119 dev_err(it66353->dev, "writing register 0x%x from 0x%x failed\n", in i2c_wr()
120 reg, client->addr); in i2c_wr()
124 dev_dbg(it66353->dev, "I2C write 0x%02x = 0x%02x\n", in i2c_wr()
128 dev_dbg(it66353->dev, in i2c_wr()
133 dev_dbg(it66353->dev, in i2c_wr()
138 dev_dbg(it66353->dev, in i2c_wr()
148 struct i2c_client *client = it66353->client; in i2c_rd()
152 msg[0].addr = client->addr; in i2c_rd()
157 msg[1].addr = client->addr; in i2c_rd()
161 err = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); in i2c_rd()
163 dev_err(it66353->dev, "reading register 0x%x from 0x%x failed\n", in i2c_rd()
164 reg, client->addr); in i2c_rd()
172 it66353->client->addr = (i2c_addr >> 1); in i2c_rd8()
180 it66353->client->addr = (i2c_addr >> 1); in it66353_i2c_read()
188 it66353->client->addr = (i2c_addr >> 1); in i2c_wr8()
196 i2c_rd8(it66353_gdev.opts.dev_opt->RxAddr, offset, &rd_data); in rx_rd8()
205 i2c_rd8(it66353_gdev.opts.dev_opt->CecAddr, offset, &rd_data); in cec_rd8()
214 i2c_rd8(it66353_gdev.opts.dev_opt->SwAddr, offset, &rd_data); in sw_rd8()
222 i2c_rd8(it66353_gdev.opts.dev_opt->SwAddr, reg, &val_p); in swAddr_updata_bit()
224 i2c_wr8(it66353_gdev.opts.dev_opt->SwAddr, reg, val_p); in swAddr_updata_bit()
231 i2c_rd8(it66353_gdev.opts.dev_opt->RxAddr, reg, &val_p); in rxAddr_updata_bit()
233 i2c_wr8(it66353_gdev.opts.dev_opt->RxAddr, reg, val_p); in rxAddr_updata_bit()
240 i2c_rd8(it66353_gdev.opts.dev_opt->CecAddr, reg, &val_p); in cecAddr_updata_bit()
242 i2c_wr8(it66353_gdev.opts.dev_opt->CecAddr, reg, val_p); in cecAddr_updata_bit()
268 mutex_lock(&it66353->poll_lock); in it66353_work_i2c_poll()
270 mutex_unlock(&it66353->poll_lock); in it66353_work_i2c_poll()
271 schedule_delayed_work(&it66353->work_i2c_poll, msecs_to_jiffies(50)); in it66353_work_i2c_poll()
279 dev_info(it66353->dev, "%s: hdmi rx select state: %d\n", in it66353_hdmirxsel_show()
280 __func__, g_it66353->hdmi_rx_sel); in it66353_hdmirxsel_show()
282 return sprintf(buf, "%d\n", g_it66353->hdmi_rx_sel); in it66353_hdmirxsel_show()
293 mutex_lock(&it66353->port_lock); in it66353_hdmirxsel_store()
296 it66353->hdmi_rx_sel = hdmirxstate; in it66353_hdmirxsel_store()
297 dev_info(it66353->dev, "%s: state: %d\n", __func__, hdmirxstate); in it66353_hdmirxsel_store()
305 dev_info(it66353->dev, "%s: write hdmi_rx_sel failed!!!, hdmirxstate:%d \n", in it66353_hdmirxsel_store()
308 mutex_unlock(&it66353->port_lock); in it66353_hdmirxsel_store()
331 struct device *dev = &client->dev; in it66353_probe()
338 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) in it66353_probe()
339 return -EIO; in it66353_probe()
340 dev_info(dev, "chip found @ 0x%x (%s)\n", client->addr << 1, in it66353_probe()
341 client->adapter->name); in it66353_probe()
344 return -ENOMEM; in it66353_probe()
346 it66353->client = client; in it66353_probe()
347 it66353->dev = dev; in it66353_probe()
348 client->flags |= I2C_CLIENT_SCCB; in it66353_probe()
350 mutex_init(&it66353->poll_lock); in it66353_probe()
351 mutex_init(&it66353->port_lock); in it66353_probe()
355 dev_err(it66353->dev, in it66353_probe()
359 INIT_DELAYED_WORK(&it66353->work_i2c_poll, it66353_work_i2c_poll); in it66353_probe()
366 dev_err(it66353->dev, "failed to create attr hdmirxsel!\n"); in it66353_probe()
370 schedule_delayed_work(&it66353->work_i2c_poll, msecs_to_jiffies(10)); in it66353_probe()
371 dev_info(it66353->dev, "%s found @ 0x%x (%s)\n", in it66353_probe()
372 client->name, client->addr << 1, in it66353_probe()
373 client->adapter->name); in it66353_probe()
382 cancel_delayed_work_sync(&it66353->work_i2c_poll); in it66353_remove()
387 mutex_destroy(&it66353->poll_lock); in it66353_remove()
388 mutex_destroy(&it66353->port_lock); in it66353_remove()
422 MODULE_AUTHOR("Wangqiang Guo <kay.guo@rock-chips.com>");
459 g_it66353->client->addr = (SWAddr >> 1); in it66353_h2swbrd()
467 g_it66353->client->addr = (SWAddr >> 1); in it66353_h2swbwr()
480 g_it66353->client->addr = (RXEDIDAddr >> 1); in it66353_h2rxedidwr()
487 g_it66353->client->addr = (RXEDIDAddr >> 1); in it66353_h2rxedidrd()
516 g_it66353->client->addr = (RXAddr >> 1); in it66353_h2rxbrd()
524 g_it66353->client->addr = (RXAddr >> 1); in it66353_h2rxbwr()
553 g_it66353->client->addr = (CecAddr >> 1); in it66353_cecbrd()
561 g_it66353->client->addr = (CecAddr >> 1); in it66353_cecbwr()
593 dev_err(g_it66353->dev, "** TX DDC Bus Sta=%02x\r\n", ddc_status); in _tx_ddcwait()
594 dev_err(g_it66353->dev, "** TX DDC Bus Wait TimeOut => "); in _tx_ddcwait()
597 dev_err(g_it66353->dev, "** DDC Bus Hang\r\n"); in _tx_ddcwait()
602 dev_err(g_it66353->dev, "** DDC NoACK\r\n"); in _tx_ddcwait()
604 dev_err(g_it66353->dev, "** DDC WaitBus\r\n"); in _tx_ddcwait()
606 dev_err(g_it66353->dev, "** DDC ArbiLose\r\n"); in _tx_ddcwait()
608 dev_err(g_it66353->dev, "** UnKnown Issue\r\n"); in _tx_ddcwait()
622 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass) { in _tx_scdc_write()
623 dev_err(g_it66353->dev, "** EnRxDDCBypass:Abort SCDC write\r\n"); in _tx_scdc_write()
628 dev_err(g_it66353->dev, "** HPD-Low:Abort SCDC write\r\n"); in _tx_scdc_write()
656 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass) { in _tx_scdc_read()
657 dev_err(g_it66353->dev, "EnRxDDCBypass:Abort SCDC read\r\n"); in _tx_scdc_read()
662 dev_err(g_it66353->dev, "HPD-Low:Abort SCDC read\r\n"); in _tx_scdc_read()
678 dev_err(g_it66353->dev, "SCDC rd %02x ddcwaitsts = %d\r\n", in _tx_scdc_read()
691 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass) { in _tx_hdcp_write()
692 dev_err(g_it66353->dev, "EnRxDDCBypass:Abort HDCP write\r\n"); in _tx_hdcp_write()
697 dev_err(g_it66353->dev, "HPD-Low:Abort HDCP write\r\n"); in _tx_hdcp_write()
722 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass) { in _tx_hdcp_read()
723 dev_err(g_it66353->dev, "EnRxDDCBypass:Abort HDCP read\r\n"); in _tx_hdcp_read()
729 dev_err(g_it66353->dev, "HPD-Low:Abort HDCP read\r\n"); in _tx_hdcp_read()
744 dev_err(g_it66353->dev, "SCDC rd %02x ddcwaitsts = %d\r\n", in _tx_hdcp_read()
749 DEBUG("HDCP read - %02X : ", offset); in _tx_hdcp_read()
767 dev_err(g_it66353->dev, "HPD-Low:Abort SCDC read\r\n"); in _tx_scdc_read_ced()
782 dev_err(g_it66353->dev, "SCDC rd ced ddcwaitsts = %d\r\n", ddcwaitsts); in _tx_scdc_read_ced()
794 if (it66353_gdev.opts.dev_opt->DoTxPowerDown) { in _tx_power_down()
819 if (ced_valid & (0x01 << i)) { // 0x5? error status is valid in _tx_show_sink_ced()
1034 if (vclk > 300000UL) { // single-end swing = 520mV in _tx_setup_afe()
1045 } else if (vclk > 100000UL) { // single-end swing = 450mV in _tx_setup_afe()
1055 } else { // single-end swing = 500mV in _tx_setup_afe()
1088 sum = sum - edid[i]; in _rx_calc_edid_sum()
1135 dev_err(g_it66353->dev, "ERROR: CAOF fail !!!\r\n"); in it66353_rx_caof_init()
1153 DEBUG("CAOF_Int=%02x, Status=%02x\r\n\r\n", in it66353_rx_caof_init()
1172 it66353_rx_auto_power_down_enable(port, it66353_gdev.opts.dev_opt->RxAutoPowerDown); in it66353_rx_caof_init()
1248 dev_info(g_it66353->dev, "HDCP 2 done\r\n"); in _rx_need_hpd_toggle()
1252 dev_info(g_it66353->dev, "HDCP 1 done\r\n"); in _rx_need_hpd_toggle()
1256 dev_info(g_it66353->dev, "HDCP acc\r\n"); in _rx_need_hpd_toggle()
1261 dev_info(g_it66353->dev, "TXOE timeout 2\r\n"); in _rx_need_hpd_toggle()
1360 if (it66353_gdev.opts.rx_opt[port]->EnRxDDCBypass == 0) { in _rx_set_hpd()
1367 if (it66353_gdev.opts.rx_opt[port]->DisableEdidRam == 0) { in _rx_set_hpd()
1371 if (it66353_gdev.opts.rx_opt[port]->HPDOutputInverse) { in _rx_set_hpd()
1403 if (it66353_gdev.opts.rx_opt[port]->HPDOutputInverse) { in _rx_set_hpd()
1413 dev_info(g_it66353->dev, "Set RxP%d HPD = %d %02x\r\n", in _rx_set_hpd()
1417 dev_err(g_it66353->dev, "Invaild port %d\r\n", port); in _rx_set_hpd()
1440 if (it66353_gdev.opts.rx_opt[i]->NonActivePortReplyHPD) { in _rx_set_hpd_with_5v_all()
1466 if (it66353_gdev.opts.active_rx_opt->EnableAutoEQ) { in it66353it66353_rx_handle_output_err()
1468 dev_info(g_it66353->dev, "*** fixed EQ fail\r\n"); in it66353it66353_rx_handle_output_err()
1607 dev_info(g_it66353->dev, "## src SCDC wr %02x\r\n", reg); in _sw_monitor_and_fix_scdc_write()
1657 // need re-calculate RDetIPLL_HS1P48G in _sw_sdi_check()
1692 if (it66353_gdev.opts.dev_opt->ForceRxOn) { in _tx_init()
1696 it66353_h2swset(0xF4, 0x80, it66353_gdev.opts.dev_opt->ForceRxOn << 7); in _tx_init()
1705 it66353_h2swset(0xA9, 0xC0, (it66353_gdev.opts.tx_opt->EnTxChSwap << 7) + in _tx_init()
1706 (it66353_gdev.opts.tx_opt->EnTxPNSwap << 6)); in _tx_init()
1714 it66353_h2swset(0xBD, 0x01, it66353_gdev.opts.tx_opt->EnTxVCLKInv); in _tx_init()
1715 it66353_h2swset(0xA9, 0x20, it66353_gdev.opts.tx_opt->EnTxOutD1t << 5); in _tx_init()
1775 it66353_h2swwr(0xEF, it66353_gdev.opts.dev_opt->RxAddr | 0x01); in _sw_init()
1782 it66353_h2swwr(0xEE, (it66353_gdev.opts.dev_opt->CecAddr | 0x01)); in _sw_init()
1791 it66353_h2swwr(0xEE, (it66353_gdev.opts.dev_opt->CecAddr | 0x01)); in _sw_init()
1795 it66353_h2swwr(0xEE, (it66353_gdev.opts.dev_opt->CecAddr & 0xFE)); in _sw_init()
1803 // Setup INT Pin: Active Low & Open-Drain in _sw_init()
1826 it66353_rx_auto_power_down_enable_all(it66353_gdev.opts.dev_opt->RxAutoPowerDown); in _sw_init()
1836 (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass << 7)+ in _sw_init()
1837 (it66353_gdev.opts.active_rx_opt->EnRxPWR5VBypass << 6)+ in _sw_init()
1838 (it66353_gdev.opts.active_rx_opt->EnRxHPDBypass << 5)); in _sw_init()
1839 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == 1) { in _sw_init()
1849 if (it66353_gdev.opts.rx_opt[port]->DisableEdidRam) { in _sw_init()
1859 if (it66353_gdev.opts.active_rx_opt->EnRxHPDBypass) { in _sw_init()
1881 it66353_h2swwr(0xEF, it66353_gdev.opts.dev_opt->RxAddr | 0x01); in _sw_reset()
1883 if (it66353_h2swrd(0xEF) == (it66353_gdev.opts.dev_opt->RxAddr | 0x01)) { in _sw_reset()
1919 timer_flt = (rclk - timer_int * 1000) * 256 / 1000; in it66353_cal_rclk()
1932 wclk_high_num = 32UL * rclk_tmp - (wclk_high_num_b * 37125UL); in it66353_cal_rclk()
1937 wclk_high_num = 4UL * rclk_tmp - (wclk_high_num_c * 10625UL); in it66353_cal_rclk()
2013 DEBUG("TXOE=%d align=%d\r\n", enable, it66353_gdev.opts.active_rx_opt->TxOEAlignment); in it66353_txoe()
2039 DEBUG("A_TXOE=%d align=%d\r\n", enable, it66353_gdev.opts.active_rx_opt->TxOEAlignment); in it66353_auto_txoe()
2076 dev_err(g_it66353->dev, "it66353_get_rx_vclk p=%u\r\n", port); in it66353_get_rx_vclk()
2099 dev_err(g_it66353->dev, "it66353_get_rx_vclk sw_reg20=%02x\r\n", in it66353_get_rx_vclk()
2104 dev_err(g_it66353->dev, in it66353_get_rx_vclk()
2122 dev_err(g_it66353->dev, "TMDSCLKSpeed == 0 p=%u\r\n", port); in it66353_get_rx_vclk()
2130 dev_err(g_it66353->dev, "it66353_get_rx_vclk p=%u\r\n", port); in it66353_get_rx_vclk()
2170 DEBUG("--RXP-%d 5V Chg => 5V = %d\r\n", port, (rddata & 0x01)); in it66353_detect_port()
2174 if (it66353_gdev.opts.rx_opt[port]->NonActivePortReplyHPD) { in it66353_detect_port()
2187 DEBUG("--RXP-%d RX Clock Valid Chg => RxCLK_Valid = %d\r\n", in it66353_detect_port()
2192 DEBUG("--RXP-%d RX Clock Stable Chg => RxCLK_Stb = %d\r\n\r\n", in it66353_detect_port()
2197 DEBUG("--RXP-%d RX Clock Frequency Change ...\r\n", port); in it66353_detect_port()
2204 DEBUG("--RXP-%d RX Clock Ratio Chg => Clk_Ratio = %d \r\n", in it66353_detect_port()
2209 DEBUG("--RXP%d RX Scrambling Enable Chg => Scr_En = %d \r\n", in it66353_detect_port()
2217 DEBUG("--RXP%d RX Scrambling Status Chg => ScrbSts = %d \r\n", in it66353_detect_port()
2222 DEBUG("--RXP%d RX HDMI2 Detected Interrupt => HDMI2DetSts = %d \r\n", in it66353_detect_port()
2233 DEBUG("--RXP%d EDID Bus Hang\r\n", port); in it66353_detect_port()
2272 if (it66353_gdev.opts.active_rx_opt->TryFixedEQFirst) { in it66353_rx_irq()
2282 DEBUG("..RX HDMIMode chg => HDMIMode = %d\r\n", in it66353_rx_irq()
2301 DEBUG("..RX CHx SymLock Chg => RxSymLock = %d\r\n", symlock); in it66353_rx_irq()
2335 if (it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc) { in it66353_rx_irq()
2345 it66353_gdev.vars.count_fsm_err--; in it66353_rx_irq()
2397 DEBUG("..RX-P%d PWR5V Chg => PWR5V = %d\r\n", port, (rddata & 0x01)); in it66353_sw_irq()
2406 DEBUG("..RXP%d RX Clock Valid Chg => RxCLK_Valid = %d\r\n", in it66353_sw_irq()
2423 DEBUG("..RXP%d RX Clock Stable Chg => RxCLK_Stb = %d\r\n\r\n", in it66353_sw_irq()
2444 DEBUG("..RXP%d RX Clock Frequency Chg ...\r\n", port); in it66353_sw_irq()
2450 DEBUG("..RXP%d RX Clock Ratio Chg => Clk_Ratio = %d \r\n", in it66353_sw_irq()
2455 it66353_auto_txoe(it66353_gdev.opts.active_rx_opt->TxOEAlignment); in it66353_sw_irq()
2469 DEBUG("..RXP%d RX Scrambling Enable Chg => Scr_En = %d \r\n", in it66353_sw_irq()
2476 DEBUG("..RXP%d RX Scrambling Status Chg => ScrbSts = %d \r\n", in it66353_sw_irq()
2510 // dev_info(g_it66353->dev, " => HDCP 0x74 is detected\r\n"); in it66353_tx_irq()
2534 DEBUG(" TX RxSen chg\r\n"); in it66353_tx_irq()
2549 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_tx_irq()
2558 // dev_info(g_it66353->dev, "SW User Timer 0 Interrupt ...\r\n"); in it66353_tx_irq()
2562 // dev_info(g_it66353->dev, "SW User Timer 1 Interrupt ...\r\n"); in it66353_tx_irq()
2567 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_tx_irq()
2578 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_tx_irq()
2610 dev_err(g_it66353->dev, "**Wait DDC idle timeout\n"); in it66353_wait_for_ddc_idle()
2628 DEBUG("state_fsm %s -> %s (%d)\r\n", in __it66353_fsm_chg()
2632 dev_err(g_it66353->dev, "state_fsm %d, new %d -> %d\r\n", in __it66353_fsm_chg()
2636 DEBUG("state_fsm %d -> %d\r\n", it66353_gdev.vars.state_sys_fsm, new_state); in __it66353_fsm_chg()
2641 DEBUG("skip fsm chg 1\r\n"); in __it66353_fsm_chg()
2650 DEBUG("skip fsm chg 2\r\n"); in __it66353_fsm_chg()
2669 it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in __it66353_fsm_chg()
2672 if (it66353_gdev.opts.tx_opt->TurnOffTx5VWhenSwitchPort) { in __it66353_fsm_chg()
2694 it66353_set_RS(it66353_gdev.opts.active_rx_opt->DefaultEQ[0], in __it66353_fsm_chg()
2695 it66353_gdev.opts.active_rx_opt->DefaultEQ[1], in __it66353_fsm_chg()
2696 it66353_gdev.opts.active_rx_opt->DefaultEQ[2]); in __it66353_fsm_chg()
2708 if ((it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc) && in __it66353_fsm_chg()
2709 (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == FALSE)) { in __it66353_fsm_chg()
2723 if ((it66353_gdev.opts.active_rx_opt->DisableEdidRam & in __it66353_fsm_chg()
2754 dev_dbg(g_it66353->dev, "Clk Ratio = %d\r\n", in __it66353_fsm_chg()
2770 #if 0 // for 8-7 480p in __it66353_fsm_chg()
2787 dev_dbg(g_it66353->dev, "Clk Ratio==0, align=0\n"); in __it66353_fsm_chg()
2789 it66353_auto_txoe(it66353_gdev.opts.active_rx_opt->TxOEAlignment); in __it66353_fsm_chg()
2790 dev_dbg(g_it66353->dev, "Clk Ratio==1, align=%d\n", in __it66353_fsm_chg()
2791 it66353_gdev.opts.active_rx_opt->TxOEAlignment); in __it66353_fsm_chg()
2801 if (it66353_gdev.opts.dev_opt->TxPowerDownWhileWaitingClock) { in __it66353_fsm_chg()
2848 if ((it66353_gdev.opts.active_rx_opt->DisableEdidRam & in __it66353_fsm_chg()
2858 it66353_auto_txoe(it66353_gdev.opts.active_rx_opt->TxOEAlignment); in __it66353_fsm_chg()
2868 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in __it66353_fsm_chg()
2882 if (it66353_gdev.opts.active_rx_opt->NonActivePortReplyHPD) { in __it66353_fsm_chg()
2939 dev_dbg(g_it66353->dev, "#state_fsm %s -> %s (%d)\r\n", in __it66353_fsm_chg2()
2943 dev_err(g_it66353->dev, "#state_fsm %d, new %d -> %d\r\n", in __it66353_fsm_chg2()
2947 dev_dbg(g_it66353->dev, "#state_fsm %d -> %d\r\n", in __it66353_fsm_chg2()
2968 dev_info(g_it66353->dev, "HDMI_MODE=AUTO \r\n"); in it66353_auto_detect_hdmi_encoding()
2977 dev_info(g_it66353->dev, "HDMI_MODE=F20\r\n"); in it66353_force_hdmi20()
2986 dev_info(g_it66353->dev, "HDMI_MODE=F14\r\n"); in it66353_force_hdmi14()
3025 dev_info(g_it66353->dev, "EQ restore2 !\r\n"); in it66353_fsm_EQ_check()
3030 dev_info(g_it66353->dev, "[%d] eq_state=%d\r\n", in it66353_fsm_EQ_check()
3039 dev_info(g_it66353->dev, "EQ done !\r\n"); in it66353_fsm_EQ_check()
3047 dev_info(g_it66353->dev, "EQ give up !\r\n"); in it66353_fsm_EQ_check()
3054 dev_info(g_it66353->dev, "EQ restore !\r\n"); in it66353_fsm_EQ_check()
3058 dev_info(g_it66353->dev, "EQ default !\r\n"); in it66353_fsm_EQ_check()
3060 dev_err(g_it66353->dev, "??eq_state=%d\r\n", eq_state); in it66353_fsm_EQ_check()
3078 if ((it66353_gdev.opts.active_rx_opt->NonActivePortReplyHPD == 0) && in it66353_fsm()
3079 (it66353_gdev.opts.tx_opt->TurnOffTx5VWhenSwitchPort == 0)) { in it66353_fsm()
3096 it66353_gdev.vars.hpd_toggle_timeout = it66353_gdev.opts.active_rx_opt->HPDTogglePeriod; in it66353_fsm()
3106 dev_err(g_it66353->dev, in it66353_fsm()
3118 dev_err(g_it66353->dev, in it66353_fsm()
3139 if (it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc) { in it66353_fsm()
3145 HDMI_MODE_AUTO && it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == in it66353_fsm()
3165 dev_err(g_it66353->dev, "RxChk-SymUnlock\r\n"); in it66353_fsm()
3171 if (it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc) { in it66353_fsm()
3203 dev_err(g_it66353->dev, in it66353_fsm()
3252 if (it66353_gdev.opts.active_rx_opt->EnableAutoEQ) { in it66353_fsm()
3361 dev_info(g_it66353->dev, "---HDCP BD=%02x\r\n", currBD); in it66353_irq()
3427 it66353_set_RS(it66353_gdev.opts.active_rx_opt->DefaultEQ[0], in it66353_device_init()
3428 it66353_gdev.opts.active_rx_opt->DefaultEQ[1], in it66353_device_init()
3429 it66353_gdev.opts.active_rx_opt->DefaultEQ[2]); in it66353_device_init()
3430 if (it66353_gdev.opts.tx_opt->CopyEDIDFromSink) { in it66353_device_init()
3441 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_device_init()
3455 dev_info(g_it66353->dev, "waiting HPD...\r\n"); in it66353_device_init()
3463 dev_info(g_it66353->dev, "Using internal EDID...\r\n"); in it66353_device_init()
3464 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == false) { in it66353_device_init()
3494 dev_info(g_it66353->dev, "Active port = P%d\r\n", in it66353_device_init()
3519 it66353_gdev.vars.RxHPDFlag[0] = -1; in it66353_vars_init()
3520 it66353_gdev.vars.RxHPDFlag[1] = -1; in it66353_vars_init()
3521 it66353_gdev.vars.RxHPDFlag[2] = -1; in it66353_vars_init()
3522 it66353_gdev.vars.RxHPDFlag[3] = -1; in it66353_vars_init()
3523 it66353_gdev.vars.Tx_current_5v = -1; in it66353_vars_init()
3537 if (it66353_gdev.opts.active_rx_opt->TryFixedEQFirst) { in it66353_vars_init()
3576 dev_info(g_it66353->dev, "Find 6635 %02x !! \r\n", in it66353_is_device_ready()
3584 dev_info(g_it66353->dev, "Find 6635x %02x !! \r\n", in it66353_is_device_ready()
3590 dev_info(g_it66353->dev, "Find 6635 fail !!\r\n"); in it66353_is_device_ready()
3626 dev_err(g_it66353->dev, "ERROR: DDC EDID Read Fail !!!\r\n"); in it66353_read_edid()
3628 retry--; in it66353_read_edid()
3634 dev_err(g_it66353->dev, in it66353_read_edid()
3644 * it66353_read_one_block_edid - will read 128 byte EDID data
3665 dev_err(g_it66353->dev, in it66353_read_one_block_edid()
3704 dev_info(g_it66353->dev, "HDMI2 sink=%d\n", it66353_gdev.vars.is_hdmi20_sink); in it66353_parse_edid_for_vsdb()
3708 * it66353_parse_edid_for_phyaddr - parse necessary data for RX
3739 (0x100 - edid[0x7F] - in it66353_parse_edid_for_phyaddr()
3740 edid[off + 4] - in it66353_parse_edid_for_phyaddr()
3761 dev_info(g_it66353->dev, "Set RX EDID step2...\r\n"); in it66353_setup_edid_ram_step2()
3770 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr | 0x01); in it66353_setup_edid_ram_step2()
3774 dev_info(g_it66353->dev, "VSDB=%02x\r\n", it66353_gdev.vars.VSDBOffset); in it66353_setup_edid_ram_step2()
3813 sum = (0x100 - it66353_gdev.vars.EdidChkSum[1] - phyAB - phyCD) & 0xFF; in it66353_setup_edid_ram_step2()
3849 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr); in it66353_setup_edid_ram_step2()
3869 dev_err(g_it66353->dev, "ERROR: DDC 0x1B=%02X\r\n", uc); in it66353_ddc_abort()
3887 if (it66353_gdev.opts.tx_opt->CopyEDIDFromSink) { in it66353_update_edid()
3890 dev_err(g_it66353->dev, "ERROR: read edid block 0\r\n"); in it66353_update_edid()
3965 if (it66353_gdev.opts.tx_opt->CopyEDIDFromSink) { in it66353_setup_edid_ram()
3975 dev_err(g_it66353->dev, "Warning: Extblock = %d\r\n", extblock); in it66353_setup_edid_ram()
3996 if (it66353_gdev.opts.tx_opt->CopyEDIDFromSink) { in it66353_setup_edid_ram()
4004 if (it66353_gdev.opts.tx_opt->ParsePhysicalAddr) { in it66353_setup_edid_ram()
4066 dev_info(g_it66353->dev, ".rx_opt->tag1=%d\r\n", in it66353_dump_opts()
4067 it66353_gdev.opts.active_rx_opt->tag1); in it66353_dump_opts()
4068 dev_info(g_it66353->dev, ".rx_opt->EnRxDDCBypass=%d\r\n", in it66353_dump_opts()
4069 it66353_gdev.opts.active_rx_opt->EnRxDDCBypass); in it66353_dump_opts()
4070 dev_info(g_it66353->dev, ".rx_opt->EnRxPWR5VBypass=%d\r\n", in it66353_dump_opts()
4071 it66353_gdev.opts.active_rx_opt->EnRxPWR5VBypass); in it66353_dump_opts()
4072 dev_info(g_it66353->dev, ".rx_opt->EnRxHPDBypass=%d\r\n", in it66353_dump_opts()
4073 it66353_gdev.opts.active_rx_opt->EnRxHPDBypass); in it66353_dump_opts()
4074 dev_info(g_it66353->dev, ".rx_opt->TryFixedEQFirst=%d\r\n", in it66353_dump_opts()
4075 it66353_gdev.opts.active_rx_opt->TryFixedEQFirst); in it66353_dump_opts()
4076 dev_info(g_it66353->dev, ".rx_opt->EnableAutoEQ=%d\r\n", in it66353_dump_opts()
4077 it66353_gdev.opts.active_rx_opt->EnableAutoEQ); in it66353_dump_opts()
4078 dev_info(g_it66353->dev, ".rx_opt->NonActivePortReplyHPD=%d\r\n", in it66353_dump_opts()
4079 it66353_gdev.opts.active_rx_opt->NonActivePortReplyHPD); in it66353_dump_opts()
4080 dev_info(g_it66353->dev, ".rx_opt->DisableEdidRam=%d\r\n", in it66353_dump_opts()
4081 it66353_gdev.opts.active_rx_opt->DisableEdidRam); in it66353_dump_opts()
4082 dev_info(g_it66353->dev, ".rx_opt->DefaultEQ=%x %x %x\r\n", in it66353_dump_opts()
4083 it66353_gdev.opts.active_rx_opt->DefaultEQ[0], in it66353_dump_opts()
4084 it66353_gdev.opts.active_rx_opt->DefaultEQ[1], in it66353_dump_opts()
4085 it66353_gdev.opts.active_rx_opt->DefaultEQ[2]); in it66353_dump_opts()
4086 dev_info(g_it66353->dev, ".rx_opt->FixIncorrectHdmiEnc=%d\r\n", in it66353_dump_opts()
4087 it66353_gdev.opts.active_rx_opt->FixIncorrectHdmiEnc); in it66353_dump_opts()
4088 dev_info(g_it66353->dev, ".rx_opt->HPDOutputInverse=%d\r\n", in it66353_dump_opts()
4089 it66353_gdev.opts.active_rx_opt->HPDOutputInverse); in it66353_dump_opts()
4090 dev_info(g_it66353->dev, ".rx_opt->HPDTogglePeriod=%d\r\n", in it66353_dump_opts()
4091 it66353_gdev.opts.active_rx_opt->HPDTogglePeriod); in it66353_dump_opts()
4092 dev_info(g_it66353->dev, ".rx_opt->TxOEAlignment=%d\r\n", in it66353_dump_opts()
4093 it66353_gdev.opts.active_rx_opt->TxOEAlignment); in it66353_dump_opts()
4094 dev_info(g_it66353->dev, ".rx_opt->str_size=%d\r\n", in it66353_dump_opts()
4095 it66353_gdev.opts.active_rx_opt->str_size); in it66353_dump_opts()
4097 dev_info(g_it66353->dev, ".tx_opt->tag1=%d\r\n", it66353_gdev.opts.tx_opt->tag1); in it66353_dump_opts()
4098 dev_info(g_it66353->dev, ".tx_opt->EnTxPNSwap=%d\r\n", in it66353_dump_opts()
4099 it66353_gdev.opts.tx_opt->EnTxPNSwap); in it66353_dump_opts()
4100 dev_info(g_it66353->dev, ".tx_opt->EnTxChSwap=%d\r\n", in it66353_dump_opts()
4101 it66353_gdev.opts.tx_opt->EnTxChSwap); in it66353_dump_opts()
4102 dev_info(g_it66353->dev, ".tx_opt->EnTxVCLKInv=%d\r\n", in it66353_dump_opts()
4103 it66353_gdev.opts.tx_opt->EnTxVCLKInv); in it66353_dump_opts()
4104 dev_info(g_it66353->dev, ".tx_opt->EnTxOutD1t=%d\r\n", in it66353_dump_opts()
4105 it66353_gdev.opts.tx_opt->EnTxOutD1t); in it66353_dump_opts()
4106 dev_info(g_it66353->dev, ".tx_opt->CopyEDIDFromSink=%d\r\n", in it66353_dump_opts()
4107 it66353_gdev.opts.tx_opt->CopyEDIDFromSink); in it66353_dump_opts()
4108 dev_info(g_it66353->dev, ".tx_opt->ParsePhysicalAddr=%d\r\n", in it66353_dump_opts()
4109 it66353_gdev.opts.tx_opt->ParsePhysicalAddr); in it66353_dump_opts()
4110 dev_info(g_it66353->dev, ".tx_opt->TurnOffTx5VWhenSwitchPort=%d\r\n", in it66353_dump_opts()
4111 it66353_gdev.opts.tx_opt->TurnOffTx5VWhenSwitchPort); in it66353_dump_opts()
4112 dev_info(g_it66353->dev, ".tx_opt->str_size=%d\r\n", in it66353_dump_opts()
4113 it66353_gdev.opts.tx_opt->str_size); in it66353_dump_opts()
4115 dev_info(g_it66353->dev, ".dev_opt->tag1=%d\r\n", in it66353_dump_opts()
4116 it66353_gdev.opts.dev_opt->tag1); in it66353_dump_opts()
4117 dev_info(g_it66353->dev, ".dev_opt->SwAddr=%d\r\n", in it66353_dump_opts()
4118 it66353_gdev.opts.dev_opt->SwAddr); in it66353_dump_opts()
4119 dev_info(g_it66353->dev, ".dev_opt->RxAddr=%d\r\n", in it66353_dump_opts()
4120 it66353_gdev.opts.dev_opt->RxAddr); in it66353_dump_opts()
4121 dev_info(g_it66353->dev, ".dev_opt->CecAddr=%d\r\n", in it66353_dump_opts()
4122 it66353_gdev.opts.dev_opt->CecAddr); in it66353_dump_opts()
4123 dev_info(g_it66353->dev, ".dev_opt->EdidAddr=%d\r\n", in it66353_dump_opts()
4124 it66353_gdev.opts.dev_opt->EdidAddr); in it66353_dump_opts()
4125 dev_info(g_it66353->dev, ".dev_opt->ForceRxOn=%d\r\n", in it66353_dump_opts()
4126 it66353_gdev.opts.dev_opt->ForceRxOn); in it66353_dump_opts()
4127 dev_info(g_it66353->dev, ".dev_opt->RxAutoPowerDown=%d\r\n", in it66353_dump_opts()
4128 it66353_gdev.opts.dev_opt->RxAutoPowerDown); in it66353_dump_opts()
4129 dev_info(g_it66353->dev, ".dev_opt->DoTxPowerDown=%d\r\n", in it66353_dump_opts()
4130 it66353_gdev.opts.dev_opt->DoTxPowerDown); in it66353_dump_opts()
4131 dev_info(g_it66353->dev, ".dev_opt->TxPowerDownWhileWaitingClock=%d\r\n", in it66353_dump_opts()
4132 it66353_gdev.opts.dev_opt->TxPowerDownWhileWaitingClock); in it66353_dump_opts()
4133 dev_info(g_it66353->dev, ".dev_opt->str_size=%d\r\n", in it66353_dump_opts()
4134 it66353_gdev.opts.dev_opt->str_size); in it66353_dump_opts()
4144 dev_info(g_it66353->dev, reg_desc); in it66353_dump_register()
4147 dev_info(g_it66353->dev, " | "); in it66353_dump_register()
4150 dev_info(g_it66353->dev, "- "); in it66353_dump_register()
4152 dev_info(g_it66353->dev, "%02X ", j); in it66353_dump_register()
4154 dev_info(g_it66353->dev, "\n"); in it66353_dump_register()
4158 dev_info(g_it66353->dev, "---"); in it66353_dump_register()
4160 dev_info(g_it66353->dev, "\n"); in it66353_dump_register()
4164 dev_info(g_it66353->dev, "%02X | ", i); in it66353_dump_register()
4168 dev_info(g_it66353->dev, "- "); in it66353_dump_register()
4170 dev_info(g_it66353->dev, "%02x ", regbuf[j]); in it66353_dump_register()
4172 dev_info(g_it66353->dev, "\n"); in it66353_dump_register()
4174 dev_info(g_it66353->dev, "\n"); in it66353_dump_register()
4179 it66353_dump_register(it66353_gdev.opts.dev_opt->SwAddr, "\n*** Switch Register:\n"); in it66353_dump_register_all()
4181 it66353_dump_register(it66353_gdev.opts.dev_opt->RxAddr, "\n*** RX Register(0):\n"); in it66353_dump_register_all()
4183 it66353_dump_register(it66353_gdev.opts.dev_opt->RxAddr, "\n*** RX Register(3):\n"); in it66353_dump_register_all()
4185 it66353_dump_register(it66353_gdev.opts.dev_opt->RxAddr, "\n*** RX Register(5):\n"); in it66353_dump_register_all()
4189 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr | 0x01); in it66353_dump_register_all()
4191 it66353_dump_register(it66353_gdev.opts.dev_opt->EdidAddr, "\n*** EDID Port 0:\n"); in it66353_dump_register_all()
4193 it66353_dump_register(it66353_gdev.opts.dev_opt->EdidAddr, "\n*** EDID Port 1:\n"); in it66353_dump_register_all()
4195 it66353_dump_register(it66353_gdev.opts.dev_opt->EdidAddr, "\n*** EDID Port 2:\n"); in it66353_dump_register_all()
4196 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr); // disable EDID RAM i2c address in it66353_dump_register_all()
4199 it66353_dump_register(it66353_gdev.opts.dev_opt->CecAddr, "\n*** CEC Register:\n"); in it66353_dump_register_all()
4228 length--; in it66353_write_edid()
4237 dev_err(g_it66353->dev, "ERROR: DDC EDID Write Fail !!!\r\n"); in it66353_write_edid()
4242 it66353_h2swset(0xF5, 0x80, (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass << 7)); in it66353_write_edid()
4243 if (it66353_gdev.opts.active_rx_opt->EnRxDDCBypass == 0) { in it66353_write_edid()
4264 dev_err(g_it66353->dev, in it66353_write_one_block_edid()
4281 dev_err(g_it66353->dev, "Invalid port number:%d\r\n", port); in it66353_is_5v_present()
4295 dev_err(g_it66353->dev, "Invalid port number:%d\r\n", port); in it66353_is_clock_detected()
4311 dev_err(g_it66353->dev, "Invalid port number:%d\r\n", port); in it66353_set_active_port()
4325 // it66353_gdev.opts.EnableAutoEQ = Opts->EnableAutoEQ; in it66353_set_option()
4326 // it66353_gdev.opts.rx_opt->EnRxDDCBypass = Opts->EnRxDDCBypass; in it66353_set_option()
4333 // Opts->EnableAutoEQ = it66353_gdev.opts.EnableAutoEQ; in it66353_get_option()
4334 // Opts->EnRxDDCBypass = it66353_gdev.opts.rx_opt->EnRxDDCBypass; in it66353_get_option()
4340 // it66353_gdev.vars.Rx_prev_port = -1; in it66353_dev_restart()
4365 dev_info(g_it66353->dev, "==> RS set to %02x %02x %02x\r\n", in it66353_set_RS()
4386 * it66353_set_internal_EDID - write data to EDID RAM
4403 dev_err(g_it66353->dev, "Invalid block %d\r\n", block); in it66353_set_internal_EDID()
4407 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr | 0x01); in it66353_set_internal_EDID()
4416 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr); in it66353_set_internal_EDID()
4420 * it66353_get_internal_EDID - read data from EDID RAM
4433 dev_err(g_it66353->dev, "Invalid block %d\r\n", block); in it66353_get_internal_EDID()
4437 dev_err(g_it66353->dev, "Invalid port %d\r\n", target_port); in it66353_get_internal_EDID()
4441 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr | 0x01); in it66353_get_internal_EDID()
4449 it66353_h2rxwr(0x4B, it66353_gdev.opts.dev_opt->EdidAddr); in it66353_get_internal_EDID()
4454 * it66353_change_default_RS - set the default RS index for each
4470 it66353_gdev.opts.rx_opt[port]->DefaultEQ[0] = new_rs_idx0; in it66353_change_default_RS()
4471 it66353_gdev.opts.rx_opt[port]->DefaultEQ[1] = new_rs_idx1; in it66353_change_default_RS()
4472 it66353_gdev.opts.rx_opt[port]->DefaultEQ[2] = new_rs_idx2; in it66353_change_default_RS()
4477 dev_err(g_it66353->dev, "Invalid port number:%d\r\n", port); in it66353_change_default_RS()
4498 if (hpd_state) { // hpd 0 --> hpd auto in it66353_force_rx_hpd()
4501 } else { // hpd auto --> hpd 0 in it66353_force_rx_hpd()