Lines Matching full:mipi
5 * it6616 HDMI to MIPI CSI-2 bridge driver.
510 struct mipi_bus mipi; member
1013 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_get_video_stable() local
1016 reg09h = it6616_mipi_tx_read(mipi, 0x09); in it6616_mipi_tx_get_video_stable()
1023 struct bus_para *bus_para = &it6616->mipi.bus_para_config; in it6616_mipitx_init_bus_para()
1193 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_get_packet_fire_state() local
1197 lp_cmd_fifo = it6616_mipi_tx_read(mipi, 0x71) & 0x0F; in it6616_mipi_tx_get_packet_fire_state()
1198 link_data_fifo = it6616_mipi_tx_read(mipi, 0x72); in it6616_mipi_tx_get_packet_fire_state()
1242 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_fire_packet() local
1244 it6616_mipi_tx_write(mipi, 0x75, dcs_setting_table[cmd_name].cmd); in it6616_mipi_tx_fire_packet()
1252 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_setup_packet_process() local
1264 it6616_mipi_tx_write(mipi, 0x73, dcs_setting_table[cmd_name].para_list[i]); in it6616_mipi_tx_setup_packet_process()
1277 it6616_mipi_tx_write(mipi, 0x73, ((u8 *)(&packet))[i]); in it6616_mipi_tx_setup_packet_process()
1292 it6616_mipi_tx_write(mipi, 0x73, dcs_setting_table[cmd_name].para_list[i]); in it6616_mipi_tx_setup_packet_process()
1297 it6616_mipi_tx_write(mipi, 0x73, (u8)long_packet_checksum); in it6616_mipi_tx_setup_packet_process()
1298 it6616_mipi_tx_write(mipi, 0x73, (u8)(long_packet_checksum >> 8)); in it6616_mipi_tx_setup_packet_process()
1309 it6616_mipi_tx_write(mipi, 0x74, (it6616->mipi_tx_enable_h_fire_packet << 7) | data_count); in it6616_mipi_tx_setup_packet_process()
1317 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_write_lp_cmds() local
1323 it6616_mipi_tx_set_bits(mipi, 0x70, 0x03, 0x03); in it6616_mipi_tx_write_lp_cmds()
1324 it6616_mipi_tx_set_bits(mipi, 0x70, 0x03, 0x00); in it6616_mipi_tx_write_lp_cmds()
1327 it6616_mipi_tx_set_bits(mipi, 0x05, 0x16, 0x16); in it6616_mipi_tx_write_lp_cmds()
1328 it6616_mipi_tx_set_bits(mipi, 0x05, 0x16, 0x10); in it6616_mipi_tx_write_lp_cmds()
1329 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x04); in it6616_mipi_tx_write_lp_cmds()
1332 it6616_mipi_tx_write(mipi, 0x3D, 0x00); in it6616_mipi_tx_write_lp_cmds()
1333 it6616_mipi_tx_write(mipi, 0x3E, enable_force_lp_mode ? 0x00 : 0x10); in it6616_mipi_tx_write_lp_cmds()
1334 it6616_mipi_tx_write(mipi, 0x3F, enable_force_lp_mode ? 0x30 : 0x90); in it6616_mipi_tx_write_lp_cmds()
1337 dev_dbg(dev, "cmd:%d tx reg09:0x%02x", i, it6616_mipi_tx_read(mipi, 0x09)); in it6616_mipi_tx_write_lp_cmds()
1368 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x00); in it6616_mipi_tx_write_lp_cmds()
1369 it6616_mipi_tx_set_bits(mipi, 0x05, 0x16, 0x00); in it6616_mipi_tx_write_lp_cmds()
1380 struct regmap *mipi = it6616->mipi_regmap; in it6616_enter_bus_turn_around() local
1384 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x04); in it6616_enter_bus_turn_around()
1386 it6616_mipi_tx_write(mipi, 0x3E, 0x10); in it6616_enter_bus_turn_around()
1387 it6616_mipi_tx_write(mipi, 0x3F, 0x90); in it6616_enter_bus_turn_around()
1389 it6616_mipi_tx_write(mipi, 0x74, it6616->mipi_tx_enable_h_fire_packet << 7); in it6616_enter_bus_turn_around()
1390 it6616_mipi_tx_write(mipi, 0x75, LP_CMD_BTA); in it6616_enter_bus_turn_around()
1393 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x00); in it6616_enter_bus_turn_around()
1400 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_read_panel() local
1407 link0_data_count = it6616_mipi_tx_read(mipi, 0x7A); in it6616_mipi_read_panel()
1410 buffer[i] = it6616_mipi_tx_read(mipi, 0x79); in it6616_mipi_read_panel()
1415 struct mipi_bus *bus = &it6616->mipi; in it6616_mipitx_get_bus_config()
1449 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipitx_setup_dsi() local
1450 struct bus_para *bus = &it6616->mipi.bus_para_config; in it6616_mipitx_setup_dsi()
1468 it6616_mipi_tx_set_bits(mipi, 0x28, 0x20, bus->tx_sel_line_start << 5); in it6616_mipitx_setup_dsi()
1504 it6616_mipi_tx_set_bits(mipi, 0x5e, 0x03, (bus->tx_vlpm_length >> 8) & 0x03); in it6616_mipitx_setup_dsi()
1505 it6616_mipi_tx_set_bits(mipi, 0x5d, 0xff, bus->tx_vlpm_length & 0xFF); in it6616_mipitx_setup_dsi()
1506 it6616_mipi_tx_set_bits(mipi, 0x5e, 0x0c, (bus->tx_hlpm_length & 0x300) >> 6); in it6616_mipitx_setup_dsi()
1507 it6616_mipi_tx_set_bits(mipi, 0x5f, 0xff, bus->tx_hlpm_length & 0xFF); in it6616_mipitx_setup_dsi()
1508 it6616_mipi_tx_set_bits(mipi, 0x5e, 0x10, bus->tx_enable_h_enter_lpm << 4); in it6616_mipitx_setup_dsi()
1509 it6616_mipi_tx_set_bits(mipi, 0x6a, 0xff, bus->p2m_delay.tx_dsi_vsync_delay); in it6616_mipitx_setup_dsi()
1510 it6616_mipi_tx_set_bits(mipi, 0x6c, 0xff, mp_hs_pretime); in it6616_mipitx_setup_dsi()
1511 it6616_mipi_tx_set_bits(mipi, 0x6d, 0xff, mp_hs_endtime); in it6616_mipitx_setup_dsi()
1512 it6616_mipi_tx_set_bits(mipi, 0x5c, 0x03, (MIPI_TX_ENABLE_DSI_EOTP_PACKET << 1) | in it6616_mipitx_setup_dsi()
1514 it6616_mipi_tx_set_bits(mipi, 0x5c, 0xf0, ((mp_vid_type & 0x30) << 2) | in it6616_mipitx_setup_dsi()
1516 it6616_mipi_tx_set_bits(mipi, 0x60, 0x0f, p2m_time_mul); in it6616_mipitx_setup_dsi()
1517 it6616_mipi_tx_set_bits(mipi, 0x61, 0x03, p2m_time_div); in it6616_mipitx_setup_dsi()
1521 …"hs_prepare_zero num: 0x%02x, hs_trail num: 0x%02x, dsi_vsync_delay: 0x%02x, mipi DSI TX setting d… in it6616_mipitx_setup_dsi()
1528 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipitx_setup_csi() local
1529 struct bus_para *bus = &it6616->mipi.bus_para_config; in it6616_mipitx_setup_csi()
1569 it6616_mipi_tx_write(mipi, 0x1F, mp_hs_endtime); in it6616_mipitx_setup_csi()
1570 it6616_mipi_tx_write(mipi, 0x22, mp_hs_pretime); in it6616_mipitx_setup_csi()
1571 it6616_mipi_tx_write(mipi, 0x24, 0x20); in it6616_mipitx_setup_csi()
1572 it6616_mipi_tx_write(mipi, 0x25, bus->p2m_delay.tx_csi_p2m_delay); in it6616_mipitx_setup_csi()
1573 it6616_mipi_tx_set_bits(mipi, 0x26, 0x20, (en_fs_fr_num << 5)); in it6616_mipitx_setup_csi()
1574 it6616_mipi_tx_write(mipi, 0x27, 0x02); in it6616_mipitx_setup_csi()
1575 it6616_mipi_tx_write(mipi, 0x20, mp_vid_type); in it6616_mipitx_setup_csi()
1576 it6616_mipi_tx_write(mipi, 0x23, reg23); in it6616_mipitx_setup_csi()
1580 …"hs_prepare_zero num: 0x%02x, hs_trail num: 0x%02x, tx_csi_p2m_delay: 0x%02x, mipi CSI TX setting … in it6616_mipitx_setup_csi()
1586 u8 i, csi_dsi_index = (it6616->mipi.bus_type == MIPI_CSI) ? 0 : 1; in it6616_mipi_tx_find_color_space_name_index()
1589 if (it6616->mipi.data_type == mipi_color_space[csi_dsi_index][i]) in it6616_mipi_tx_find_color_space_name_index()
1598 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipitx_output_disable() local
1600 it6616_mipi_tx_write(mipi, 0x05, 0x36); in it6616_mipitx_output_disable()
1605 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_output_enable() local
1608 it6616_mipi_tx_write(mipi, 0x05, 0x00); in it6616_mipi_tx_output_enable()
1613 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_non_continuous_clock_setup() local
1617 it6616_mipi_tx_set_bits(mipi, 0x44, 0x01, 0x00); in it6616_mipi_tx_non_continuous_clock_setup()
1619 dev_info(dev, "set mipi tx non continuous clock"); in it6616_mipi_tx_non_continuous_clock_setup()
1624 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipitx_output_setup() local
1625 struct bus_para *bus = &it6616->mipi.bus_para_config; in it6616_mipitx_output_setup()
1629 u8 bus_type_index = ((it6616->mipi.bus_type == MIPI_CSI) ? 0 : 1); in it6616_mipitx_output_setup()
1635 it6616->mipi.lane_cnt = it6616->csi_lanes_in_use; in it6616_mipitx_output_setup()
1641 dev_info(dev, "lan_num: %d, swap_pn: %d", it6616->mipi.lane_cnt, bus->swap_pn); in it6616_mipitx_output_setup()
1670 it6616->mipi.lane_cnt = (it6616->mipi.lane_cnt == 4) ? 2 : 1; in it6616_mipitx_output_setup()
1672 MIPI_TX_LANE_ADJUST_THRESHOLD, it6616->mipi.lane_cnt); in it6616_mipitx_output_setup()
1680 it6616_mipi_tx_set_bits(mipi, 0x28, 0x0c, (bus->swap_pn << 3) | (bus->swap_lan << 2)); in it6616_mipitx_output_setup()
1681 it6616_mipi_tx_set_bits(mipi, 0x10, BIT(2), bus->pclk_inv << 2); in it6616_mipitx_output_setup()
1683 switch (it6616_mipi_tx_read(mipi, 0x04)) { in it6616_mipitx_output_setup()
1685 it6616_mipi_tx_set_bits(mipi, 0x10, BIT(1), bus->mclk_inv << 1); in it6616_mipitx_output_setup()
1688 it6616_mipi_tx_set_bits(mipi, 0x11, BIT(3), bus->mclk_inv << 3); in it6616_mipitx_output_setup()
1691 it6616_mipi_tx_set_bits(mipi, 0x8c, 0x40, 0x00); in it6616_mipitx_output_setup()
1692 it6616_mipi_tx_set_bits(mipi, 0x47, 0xf0, bus->mipi_tx_hs_prepare << 4); in it6616_mipitx_output_setup()
1693 it6616_mipi_tx_set_bits(mipi, 0x44, 0x04, bus->tx_enable_hs_pre_1T << 2); in it6616_mipitx_output_setup()
1694 it6616_mipi_tx_set_bits(mipi, 0x21, 0x30, (it6616->mipi.lane_cnt - 1) << 4); in it6616_mipitx_output_setup()
1703 if (it6616->mipi.bus_type == MIPI_CSI) { in it6616_mipitx_output_setup()
1732 /* setup mipi-tx-afe */ in it6616_mipitx_output_setup()
1733 it6616_mipi_tx_write(mipi, 0xb0, regb0); in it6616_mipitx_output_setup()
1753 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_get_support_format() local
1755 u8 mipi_intput_color = it6616->mipi.data_type; in it6616_mipi_tx_get_support_format()
1757 u8 bus_type_index = ((it6616->mipi.bus_type == MIPI_CSI) ? 0 : 1); in it6616_mipi_tx_get_support_format()
1759 if (it6616->mipi.bus_type == MIPI_CSI) { in it6616_mipi_tx_get_support_format()
1763 it6616->mipi.data_type = CSI_RGB888; in it6616_mipi_tx_get_support_format()
1768 it6616->mipi.data_type = CSI_YCbCr4228b; in it6616_mipi_tx_get_support_format()
1784 if (it6616_mipi_tx_read(mipi, 0x04) == 0xC0) { in it6616_mipi_tx_get_support_format()
1788 mipi_intput_color = it6616->mipi.data_type = DSI_RGB_24b; in it6616_mipi_tx_get_support_format()
1789 dev_dbg(dev, "0xC0 MIPI DSI only support RGB, using: DSI_RGB_24b(%d)", in it6616_mipi_tx_get_support_format()
1797 * mipi rx need pn swap and let first bit data(after SOT) will be rising edge
1802 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_rk_fix_first_bit_issue() local
1804 it6616_mipi_tx_write(mipi, 0x05, 0x00); in it6616_mipi_tx_rk_fix_first_bit_issue()
1805 it6616_mipi_tx_set_bits(mipi, 0x28, 0x08, 0x08); in it6616_mipi_tx_rk_fix_first_bit_issue()
1806 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x04); in it6616_mipi_tx_rk_fix_first_bit_issue()
1807 it6616_mipi_tx_set_bits(mipi, 0x28, 0x08, 0x00); in it6616_mipi_tx_rk_fix_first_bit_issue()
1808 it6616_mipi_tx_set_bits(mipi, 0x70, 0x04, 0x00); in it6616_mipi_tx_rk_fix_first_bit_issue()
1809 it6616_mipi_tx_write(mipi, 0x05, 0x36); in it6616_mipi_tx_rk_fix_first_bit_issue()
1814 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipitx_initial() local
1816 struct bus_para *bus = &it6616->mipi.bus_para_config; in it6616_mipitx_initial()
1818 it6616_mipi_tx_set_bits(mipi, 0x05, 0x09, 0x09); in it6616_mipitx_initial()
1819 it6616_mipi_tx_write(mipi, 0x05, 0x36); in it6616_mipitx_initial()
1821 it6616_mipi_tx_set_bits(mipi, 0x2A, 0x3c, 0x00); in it6616_mipitx_initial()
1822 it6616_mipi_tx_set_bits(mipi, 0x3c, 0x20, 0x20); in it6616_mipitx_initial()
1823 it6616_mipi_tx_set_bits(mipi, 0x6b, 0x01, it6616->mipi.bus_type); in it6616_mipitx_initial()
1824 it6616_mipi_tx_set_bits(mipi, 0x10, 0x80, bus->tx_bypass << 7); in it6616_mipitx_initial()
1825 it6616_mipi_tx_set_bits(mipi, 0xc1, 0x03, 0x03); in it6616_mipitx_initial()
1826 it6616_mipi_tx_set_bits(mipi, 0xa8, 0x01, 0x00); in it6616_mipitx_initial()
1827 it6616_mipi_tx_set_bits(mipi, 0x45, 0x0f, bus->lpx_num); in it6616_mipitx_initial()
1832 it6616_mipi_tx_write(mipi, 0x05, 0x36); in it6616_mipitx_initial()
1835 dev_dbg(dev, "mipi_initial chip:0x%02x", it6616_mipi_tx_read(mipi, 0x04)); in it6616_mipitx_initial()
1883 u8 mipi_intput_color = it6616->mipi.data_type; in it6616_hdmi_get_output_color_space()
1885 if (it6616->mipi.bus_type == MIPI_CSI) { in it6616_hdmi_get_output_color_space()
2188 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_calc_rclk() local
2194 it6616_mipi_tx_set_bits(mipi, 0xE0, 0x80, 0x80); // Enable RCLK 100ms count in it6616_mipi_tx_calc_rclk()
2196 it6616_mipi_tx_set_bits(mipi, 0xE0, 0x80, 0x00); // Disable RCLK 100ms count in it6616_mipi_tx_calc_rclk()
2198 ul100msCNT = it6616_mipi_tx_read(mipi, 0xE3); in it6616_mipi_tx_calc_rclk()
2199 ul100msCNT = ((ul100msCNT << 8) | (it6616_mipi_tx_read(mipi, 0xE2))); in it6616_mipi_tx_calc_rclk()
2200 ul100msCNT = ((ul100msCNT << 8) | (it6616_mipi_tx_read(mipi, 0xE1))); in it6616_mipi_tx_calc_rclk()
2207 dev_dbg(dev, "mipi rclk = %d.%d MHz", it6616->tx_rclk / 1000, in it6616_mipi_tx_calc_rclk()
2213 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_calc_mclk() local
2219 it6616_mipi_tx_set_bits(mipi, 0xE7, 0x80, 0x80); in it6616_mipi_tx_calc_mclk()
2221 it6616_mipi_tx_set_bits(mipi, 0xE7, 0x80, 0x00); in it6616_mipi_tx_calc_mclk()
2223 ulCNT = it6616_mipi_tx_read(mipi, 0xE7) & 0x0F; in it6616_mipi_tx_calc_mclk()
2224 ulCNT = (it6616_mipi_tx_read(mipi, 0xE6) | (ulCNT << 8)); in it6616_mipi_tx_calc_mclk()
2234 dev_dbg(dev, "mipi mclk = %lu.%lu MHz", tx_mclk / 1000, tx_mclk % 1000); in it6616_mipi_tx_calc_mclk()
2239 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipi_tx_calc_pclk() local
2245 it6616_mipi_tx_set_bits(mipi, 0xE5, 0x80, 0x80); in it6616_mipi_tx_calc_pclk()
2247 it6616_mipi_tx_set_bits(mipi, 0xE5, 0x80, 0x00); in it6616_mipi_tx_calc_pclk()
2249 ulCNT = it6616_mipi_tx_read(mipi, 0xE5) & 0x0F; in it6616_mipi_tx_calc_pclk()
2250 ulCNT = it6616_mipi_tx_read(mipi, 0xE4) + (ulCNT << 8); in it6616_mipi_tx_calc_pclk()
2260 dev_dbg(dev, "mipi pclk = %u.%u MHz", it6616->tx_pclk / 1000, in it6616_mipi_tx_calc_pclk()
2500 if (it6616->mipi.bus_type == MIPI_CSI) { in it6616_hdmi_rx_setup_csc()
2501 switch (it6616->mipi.data_type) { in it6616_hdmi_rx_setup_csc()
2507 switch (it6616->mipi.data_type) { in it6616_hdmi_rx_setup_csc()
2756 struct regmap *mipi = it6616->mipi_regmap; in it6616_mipitx_irq() local
2760 reg09h = it6616_mipi_tx_read(mipi, 0x09); in it6616_mipitx_irq()
2761 reg0ah = it6616_mipi_tx_read(mipi, 0x0A); in it6616_mipitx_irq()
2762 reg0bh = it6616_mipi_tx_read(mipi, 0x0B); in it6616_mipitx_irq()
2764 it6616_mipi_tx_write(mipi, 0x0A, reg0ah); in it6616_mipitx_irq()
2765 it6616_mipi_tx_write(mipi, 0x0B, reg0bh); in it6616_mipitx_irq()
2769 dev_info(dev, "mipi tx Video Stable Change ..."); in it6616_mipitx_irq()
2770 dev_info(dev, "mipi tx reg09 = 0x%02x, video %sstable", in it6616_mipitx_irq()
2782 dev_err(dev, "Mipi Byte mismatch Err!!!\n"); in it6616_mipitx_irq()
2784 dev_err(dev, "mipi P2M FIFO Err!!!\n"); in it6616_mipitx_irq()
3062 // mipi common settings: in it6616_initial()
3063 it6616->mipi.bus_type = MIPI_TX_INTERFACE; in it6616_initial()
3064 it6616->mipi.lane_cnt = it6616->csi_lanes_in_use; in it6616_initial()
3065 it6616->mipi.data_type = MIPI_TX_DATA_TYPE; in it6616_initial()
3255 struct regmap *mipi = it6616->mipi_regmap; in mipi_reg_show() local
3261 reg_buf[i] = it6616_mipi_tx_read(mipi, i); in mipi_reg_show()
3262 //regmap_bulk_read(mipi, 0, reg_buf, 256); in mipi_reg_show()
3272 struct regmap *mipi = it6616->mipi_regmap; in mipi_reg_store() local
3281 regmap_write(mipi, addr, val); in mipi_reg_store()