56 	struct clk		*xvclk;  member
72 /* PLL settings bases on 28M xvclk, resolution 720x480 30fps*/
236 	if (!IS_ERR(adv7181->xvclk)) {  in __adv7181_power_on()
237 		ret = clk_prepare_enable(adv7181->xvclk);  in __adv7181_power_on()
239 			dev_err(dev, "Failed to enable xvclk\n");  in __adv7181_power_on()
257 	if (!IS_ERR(adv7181->xvclk))  in __adv7181_power_on()
258 		clk_disable_unprepare(adv7181->xvclk);  in __adv7181_power_on()
265 	if (!IS_ERR(adv7181->xvclk))  in __adv7181_power_off()
266 		clk_disable_unprepare(adv7181->xvclk);  in __adv7181_power_off()
434 	adv7181->xvclk = devm_clk_get(dev, "xvclk");  in adv7181_probe()
435 	if (!IS_ERR(adv7181->xvclk)) {  in adv7181_probe()
436 		ret = clk_set_rate(adv7181->xvclk, ADV7181_XVCLK_FREQ);  in adv7181_probe()
438 			dev_err(dev, "Failed to set xvclk rate (24MHz)\n");  in adv7181_probe()
441 		if (clk_get_rate(adv7181->xvclk) != ADV7181_XVCLK_FREQ)  in adv7181_probe()
442 			dev_warn(dev, "xvclk mismatched, it requires 24MHz\n");  in adv7181_probe()