Lines Matching refs:adv7180_write
235 static int adv7180_write(struct adv7180_state *state, unsigned int reg, in adv7180_write() function
497 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); in adv7180_set_power()
548 ret = adv7180_write(state, ADV7180_REG_BRI, val); in adv7180_s_ctrl()
552 ret = adv7180_write(state, ADV7180_REG_HUE, -val); in adv7180_s_ctrl()
555 ret = adv7180_write(state, ADV7180_REG_CON, val); in adv7180_s_ctrl()
562 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); in adv7180_s_ctrl()
565 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); in adv7180_s_ctrl()
570 adv7180_write(state, 0x80d9, 0x44); in adv7180_s_ctrl()
571 adv7180_write(state, ADV7180_REG_FLCONTROL, in adv7180_s_ctrl()
575 adv7180_write(state, 0x80d9, 0xc4); in adv7180_s_ctrl()
576 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); in adv7180_s_ctrl()
894 adv7180_write(state, ADV7180_REG_ICR3, isr3); in adv7180_irq()
914 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, in adv7180_init()
920 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, in adv7180_init()
926 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, in adv7180_set_std()
940 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); in adv7180_select_input()
946 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, in adv7182_init()
950 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, in adv7182_init()
955 adv7180_write(state, 0x0080, 0x51); in adv7182_init()
956 adv7180_write(state, 0x0081, 0x51); in adv7182_init()
957 adv7180_write(state, 0x0082, 0x68); in adv7182_init()
962 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e); in adv7182_init()
963 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57); in adv7182_init()
964 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0); in adv7182_init()
967 adv7180_write(state, in adv7182_init()
971 adv7180_write(state, in adv7182_init()
974 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c); in adv7182_init()
975 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40); in adv7182_init()
978 adv7180_write(state, 0x0013, 0x00); in adv7182_init()
985 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4); in adv7182_set_std()
1047 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); in adv7182_select_input()
1052 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00); in adv7182_select_input()
1053 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff); in adv7182_select_input()
1061 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41); in adv7182_select_input()
1064 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01); in adv7182_select_input()
1074 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]); in adv7182_select_input()
1078 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8); in adv7182_select_input()
1079 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90); in adv7182_select_input()
1080 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0); in adv7182_select_input()
1081 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08); in adv7182_select_input()
1082 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0); in adv7182_select_input()
1084 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0); in adv7182_select_input()
1085 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0); in adv7182_select_input()
1086 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10); in adv7182_select_input()
1087 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c); in adv7182_select_input()
1088 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00); in adv7182_select_input()
1267 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); in init_device()
1283 ret = adv7180_write(state, ADV7180_REG_ICONF1, in init_device()
1289 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); in init_device()
1293 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); in init_device()
1298 ret = adv7180_write(state, ADV7180_REG_IMR3, in init_device()
1303 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); in init_device()