Lines Matching refs:vth

128 	u8    vth[6];  member
972 state->vth[0] = 0xd7; in set_vth_default()
973 state->vth[1] = 0x85; in set_vth_default()
974 state->vth[2] = 0x58; in set_vth_default()
975 state->vth[3] = 0x3a; in set_vth_default()
976 state->vth[4] = 0x34; in set_vth_default()
977 state->vth[5] = 0x28; in set_vth_default()
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth_default()
979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth_default()
980 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth_default()
981 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth_default()
982 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth_default()
983 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth_default()
1003 s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table), in set_vth() local
1007 if (state->vth[i] > vth) in set_vth()
1008 state->vth[i] = vth; in set_vth()
1010 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth()
1011 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth()
1012 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth()
1013 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth()
1014 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth()
1015 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth()