Lines Matching refs:regoff
94 u16 regoff; member
486 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3); in get_cur_symbol_rate()
487 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2); in get_cur_symbol_rate()
488 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1); in get_cur_symbol_rate()
489 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0); in get_cur_symbol_rate()
490 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2); in get_cur_symbol_rate()
491 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1); in get_cur_symbol_rate()
492 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0); in get_cur_symbol_rate()
518 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_signal_parameters()
524 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_signal_parameters()
554 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp); in tracking_optimization()
568 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); in tracking_optimization()
582 state->regoff, aclc); in tracking_optimization()
585 state->regoff, 0x2a); in tracking_optimization()
587 state->regoff, aclc); in tracking_optimization()
590 state->regoff, 0x2a); in tracking_optimization()
592 state->regoff, aclc); in tracking_optimization()
595 state->regoff, 0x2a); in tracking_optimization()
597 state->regoff, aclc); in tracking_optimization()
654 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff, in get_signal_to_noise()
656 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff, in get_signal_to_noise()
661 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff, in get_signal_to_noise()
663 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff, in get_signal_to_noise()
679 RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s()
693 state->regoff, in get_bit_error_rate_s()
699 state->regoff, 0x20 | in get_bit_error_rate_s()
753 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s2()
768 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
773 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
869 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in stop()
871 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); in stop()
873 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); in stop()
875 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); in stop()
877 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); in stop()
890 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, in set_pls()
892 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, in set_pls()
894 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, in set_pls()
908 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, in set_isi()
910 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); in set_isi()
967 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val); in enable_puncture_rate()
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth_default()
979 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth_default()
980 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth_default()
981 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth_default()
982 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth_default()
983 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth_default()
1000 RSTV0910_P2_NNOSDATAT1 + state->regoff, in set_vth()
1010 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth()
1011 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth()
1012 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth()
1013 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth()
1014 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth()
1015 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth()
1033 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); in start()
1059 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff, in start()
1061 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); in start()
1064 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits); in start()
1067 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd); in start()
1068 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, in start()
1075 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); in start()
1076 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); in start()
1081 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); in start()
1082 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); in start()
1083 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); in start()
1084 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); in start()
1085 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); in start()
1086 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); in start()
1088 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); in start()
1089 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); in start()
1090 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); in start()
1091 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); in start()
1102 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1104 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); in start()
1112 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, in start()
1114 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff)); in start()
1117 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff, in start()
1119 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff)); in start()
1122 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); in start()
1123 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); in start()
1125 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1127 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); in start()
1306 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff, in manage_matype_info()
1361 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2); in read_signal_strength()
1366 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2); in read_signal_strength()
1390 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state); in read_status()
1393 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus); in read_status()
1423 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1426 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1428 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1436 RSTV0910_P2_PDELSTATUS1 + state->regoff, in read_status()
1443 RSTV0910_P2_VSTATUSVIT + state->regoff, in read_status()
1466 RSTV0910_P2_DEMOD + state->regoff, in read_status()
1469 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1474 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1479 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1487 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1495 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1500 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); in read_status()
1506 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); in read_status()
1519 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, in read_status()
1579 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_frontend()
1585 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_frontend()
1793 state->regoff = state->nr ? 0 : 0x200; in stv0910_attach()