Lines Matching refs:cfg
99 struct _iohandle cfg; member
271 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL); in diva_irq()
289 val = readb(hw->cfg.p); in diva20x_irq()
296 writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */ in diva20x_irq()
308 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS); in tiger_irq()
326 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR); in elsa_irq()
344 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
349 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
395 writel(PITA_INT0_ENABLE, hw->cfg.p); in enable_hwirq()
399 outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in enable_hwirq()
402 outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
405 outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
408 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
410 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
413 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
415 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
419 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
423 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
439 writel(0, hw->cfg.p); in disable_hwirq()
443 outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in disable_hwirq()
446 outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
449 outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
452 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
454 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
457 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
459 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
463 outb(0, (u32)hw->cfg.start + GAZEL_INCSR); in disable_hwirq()
492 outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
494 outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
497 outb(9, (u32)hw->cfg.start + 0x69); in reset_inf()
499 (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
503 hw->cfg.p + PITA_MISC_REG); in reset_inf()
505 writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG); in reset_inf()
510 hw->cfg.p + PITA_MISC_REG); in reset_inf()
513 hw->cfg.p + PITA_MISC_REG); in reset_inf()
533 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
535 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
537 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
539 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
543 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
545 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
548 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
555 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
557 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
560 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
632 if (hw->cfg.mode) { in release_io()
633 if (hw->cfg.mode == AM_MEMIO) { in release_io()
634 release_mem_region(hw->cfg.start, hw->cfg.size); in release_io()
635 if (hw->cfg.p) in release_io()
636 iounmap(hw->cfg.p); in release_io()
638 release_region(hw->cfg.start, hw->cfg.size); in release_io()
639 hw->cfg.mode = AM_NONE; in release_io()
658 hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar); in setup_io()
659 hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar); in setup_io()
661 if (!request_mem_region(hw->cfg.start, hw->cfg.size, in setup_io()
665 if (!request_region(hw->cfg.start, hw->cfg.size, in setup_io()
672 (ulong)hw->cfg.start, (ulong)hw->cfg.size); in setup_io()
675 hw->cfg.mode = hw->ci->cfg_mode; in setup_io()
677 hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size); in setup_io()
678 if (!hw->cfg.p) in setup_io()
683 hw->name, (ulong)hw->cfg.start, in setup_io()
684 (ulong)hw->cfg.size, hw->ci->cfg_mode); in setup_io()
722 hw->isac.mode = hw->cfg.mode; in setup_io()
723 hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE; in setup_io()
724 hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT; in setup_io()
725 hw->hscx.mode = hw->cfg.mode; in setup_io()
726 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE; in setup_io()
727 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT; in setup_io()
748 hw->isac.mode = hw->cfg.mode; in setup_io()
749 hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
750 hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
751 hw->hscx.mode = hw->cfg.mode; in setup_io()
752 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
753 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
754 outb(0xff, (ulong)hw->cfg.start); in setup_io()
756 outb(0x00, (ulong)hw->cfg.start); in setup_io()
758 outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL); in setup_io()