43 	struct irq_chip_generic		*gc;  member
53 	struct irq_chip_generic *gc = handler->priv->gc;  in liointc_chained_handle_irq()  local
58 	pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);  in liointc_chained_handle_irq()
63 			(handler->parent_int_map & gc->mask_cache &  in liointc_chained_handle_irq()
73 		generic_handle_irq(irq_find_mapping(gc->domain, bit));  in liointc_chained_handle_irq()
80 static void liointc_set_bit(struct irq_chip_generic *gc,  in liointc_set_bit()  argument
85 		writel(readl(gc->reg_base + offset) | mask,  in liointc_set_bit()
86 				gc->reg_base + offset);  in liointc_set_bit()
88 		writel(readl(gc->reg_base + offset) & ~mask,  in liointc_set_bit()
89 				gc->reg_base + offset);  in liointc_set_bit()
94 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);  in liointc_set_type()  local
98 	irq_gc_lock_irqsave(gc, flags);  in liointc_set_type()
101 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);  in liointc_set_type()
102 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);  in liointc_set_type()
105 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);  in liointc_set_type()
106 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);  in liointc_set_type()
109 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);  in liointc_set_type()
110 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);  in liointc_set_type()
113 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);  in liointc_set_type()
114 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);  in liointc_set_type()
117 		irq_gc_unlock_irqrestore(gc, flags);  in liointc_set_type()
120 	irq_gc_unlock_irqrestore(gc, flags);  in liointc_set_type()
126 static void liointc_resume(struct irq_chip_generic *gc)  in liointc_resume()  argument
128 	struct liointc_priv *priv = gc->private;  in liointc_resume()
132 	irq_gc_lock_irqsave(gc, flags);  in liointc_resume()
134 	writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);  in liointc_resume()
137 		writeb(priv->map_cache[i], gc->reg_base + i);  in liointc_resume()
139 	writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);  in liointc_resume()
140 	irq_gc_unlock_irqrestore(gc, flags);  in liointc_resume()
148 	struct irq_chip_generic *gc;  in liointc_of_init()  local
233 	gc = irq_get_domain_generic_chip(domain, 0);  in liointc_of_init()
234 	gc->private = priv;  in liointc_of_init()
235 	gc->reg_base = base;  in liointc_of_init()
236 	gc->domain = domain;  in liointc_of_init()
237 	gc->resume = liointc_resume;  in liointc_of_init()
239 	ct = gc->chip_types;  in liointc_of_init()
247 	gc->mask_cache = 0;  in liointc_of_init()
248 	priv->gc = gc;  in liointc_of_init()