37 #define REG_MMU_PT_BASE_ADDR			0x000
39 #define F_ALL_INVLD				0x2
40 #define F_MMU_INV_RANGE				0x1
41 #define F_INVLD_EN0				BIT(0)
44 #define F_MMU_FAULT_VA_MSK			0xfffff000
47 #define REG_MMU_CTRL_REG			0x210
49 #define REG_MMU_IVRP_PADDR			0x214
50 #define REG_MMU_INT_CONTROL			0x220
51 #define F_INT_TRANSLATION_FAULT			BIT(0)
60 #define F_MMU_TF_PROTECT_SEL(prot)		(((prot) & 0x3) << 5)
63 #define REG_MMU_FAULT_ST			0x224
64 #define REG_MMU_FAULT_VA			0x228
65 #define REG_MMU_INVLD_PA			0x22C
66 #define REG_MMU_INT_ID				0x388
67 #define REG_MMU_INVALIDATE			0x5c0
68 #define REG_MMU_INVLD_START_A			0x5c4
69 #define REG_MMU_INVLD_END_A			0x5c8
71 #define REG_MMU_INV_SEL				0x5d8
72 #define REG_MMU_STANDARD_AXI_MODE		0x5e8
74 #define REG_MMU_DCM				0x5f0
76 #define REG_MMU_CPE_DONE			0x60c
77 #define F_DESC_VALID				0x2
79 #define MT2701_M4U_TF_LARB(TF)			(6 - (((TF) >> 13) & 0x7))
80 #define MT2701_M4U_TF_PORT(TF)			(((TF) >> 8) & 0xF)
113 	for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)  in mt2701_m4u_to_larb()
117 	return 0;  in mt2701_m4u_to_larb()
150 				tmp, tmp != 0, 10, 100000);  in mtk_iommu_tlb_flush_range()
157 	writel_relaxed(0, data->base + REG_MMU_CPE_DONE);  in mtk_iommu_tlb_flush_range()
184 			"fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",  in mtk_iommu_isr()
206 	for (i = 0; i < fwspec->num_ids; ++i) {  in mtk_iommu_config()
236 	return 0;  in mtk_iommu_domain_finalise()
274 		return 0;  in mtk_iommu_attach_device()
286 	return 0;  in mtk_iommu_attach_device()
306 	int map_size = 0;  in mtk_iommu_map()
309 	for (i = 0; i < page_num; i++) {  in mtk_iommu_map()
311 			memset(pgt_base_iova, 0, i * sizeof(u32));  in mtk_iommu_map()
323 	return map_size == size ? 0 : -EEXIST;  in mtk_iommu_map()
336 	memset(pgt_base_iova, 0, page_num * sizeof(u32));  in mtk_iommu_unmap()
407 						0, 1ULL << 32);  in mtk_iommu_create_mapping()
414 	return 0;  in mtk_iommu_create_mapping()
507 	if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,  in mtk_iommu_hw_init()
509 		writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);  in mtk_iommu_hw_init()
515 	return 0;  in mtk_iommu_hw_init()
531 	.pgsize_bitmap	= ~0UL << MT2701_IOMMU_PAGE_SHIFT,
568 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in mtk_iommu_probe()
573 	data->irq = platform_get_irq(pdev, 0);  in mtk_iommu_probe()
574 	if (data->irq < 0)  in mtk_iommu_probe()
581 	larb_nr = 0;  in mtk_iommu_probe()
583 			"mediatek,larbs", NULL, 0) {  in mtk_iommu_probe()
648 	return 0;  in mtk_iommu_remove()
662 	return 0;  in mtk_iommu_suspend()
678 	return 0;  in mtk_iommu_resume()