Lines Matching +full:mt8173 +full:- +full:smi +full:- +full:common
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
11 #include <linux/dma-direct.h>
12 #include <linux/dma-iommu.h>
31 #include <soc/mediatek/smi.h>
124 ((((pdata)->flags) & (_x)) == (_x))
150 * |---A---|---B---|---C---|---D---|---E---|
151 * +--I/O--+------------Memory-------------+
157 * |---E---|---B---|---C---|---D---|
158 * +------------Memory-------------+
215 if (pm_runtime_get_if_in_use(data->dev) <= 0) in mtk_iommu_tlb_flush_all()
219 data->base + data->plat_data->inv_sel_reg); in mtk_iommu_tlb_flush_all()
220 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); in mtk_iommu_tlb_flush_all()
223 pm_runtime_put(data->dev); in mtk_iommu_tlb_flush_all()
231 bool has_pm = !!data->dev->pm_domain; in mtk_iommu_tlb_flush_range_sync()
238 if (pm_runtime_get_if_in_use(data->dev) <= 0) in mtk_iommu_tlb_flush_range_sync()
242 spin_lock_irqsave(&data->tlb_lock, flags); in mtk_iommu_tlb_flush_range_sync()
244 data->base + data->plat_data->inv_sel_reg); in mtk_iommu_tlb_flush_range_sync()
247 data->base + REG_MMU_INVLD_START_A); in mtk_iommu_tlb_flush_range_sync()
248 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), in mtk_iommu_tlb_flush_range_sync()
249 data->base + REG_MMU_INVLD_END_A); in mtk_iommu_tlb_flush_range_sync()
251 data->base + REG_MMU_INVALIDATE); in mtk_iommu_tlb_flush_range_sync()
254 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, in mtk_iommu_tlb_flush_range_sync()
257 dev_warn(data->dev, in mtk_iommu_tlb_flush_range_sync()
262 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); in mtk_iommu_tlb_flush_range_sync()
263 spin_unlock_irqrestore(&data->tlb_lock, flags); in mtk_iommu_tlb_flush_range_sync()
266 pm_runtime_put(data->dev); in mtk_iommu_tlb_flush_range_sync()
273 struct mtk_iommu_domain *dom = data->m4u_dom; in mtk_iommu_isr()
280 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); in mtk_iommu_isr()
282 regval = readl_relaxed(data->base + REG_MMU0_INT_ID); in mtk_iommu_isr()
283 fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); in mtk_iommu_isr()
284 fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); in mtk_iommu_isr()
286 regval = readl_relaxed(data->base + REG_MMU1_INT_ID); in mtk_iommu_isr()
287 fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); in mtk_iommu_isr()
288 fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); in mtk_iommu_isr()
292 if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) { in mtk_iommu_isr()
301 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { in mtk_iommu_isr()
307 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; in mtk_iommu_isr()
309 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, in mtk_iommu_isr()
312 data->dev, in mtk_iommu_isr()
319 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); in mtk_iommu_isr()
321 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); in mtk_iommu_isr()
331 const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; in mtk_iommu_get_domain_id()
332 const struct bus_dma_region *dma_rgn = dev->dma_range_map; in mtk_iommu_get_domain_id()
333 int i, candidate = -1; in mtk_iommu_get_domain_id()
336 if (!dma_rgn || plat_data->iova_region_nr == 1) in mtk_iommu_get_domain_id()
339 dma_end = dma_rgn->dma_start + dma_rgn->size - 1; in mtk_iommu_get_domain_id()
340 for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { in mtk_iommu_get_domain_id()
342 if (dma_rgn->dma_start == rgn->iova_base && in mtk_iommu_get_domain_id()
343 dma_end == rgn->iova_base + rgn->size - 1) in mtk_iommu_get_domain_id()
346 if (dma_rgn->dma_start >= rgn->iova_base && in mtk_iommu_get_domain_id()
347 dma_end < rgn->iova_base + rgn->size) in mtk_iommu_get_domain_id()
354 &dma_rgn->dma_start, dma_rgn->size); in mtk_iommu_get_domain_id()
355 return -EINVAL; in mtk_iommu_get_domain_id()
367 for (i = 0; i < fwspec->num_ids; ++i) { in mtk_iommu_config()
368 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); in mtk_iommu_config()
369 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); in mtk_iommu_config()
371 larb_mmu = &data->larb_imu[larbid]; in mtk_iommu_config()
373 region = data->plat_data->iova_region + domid; in mtk_iommu_config()
374 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); in mtk_iommu_config()
377 enable ? "enable" : "disable", dev_name(larb_mmu->dev), in mtk_iommu_config()
378 portid, domid, larb_mmu->bank[portid]); in mtk_iommu_config()
381 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); in mtk_iommu_config()
383 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); in mtk_iommu_config()
394 if (data->m4u_dom) { in mtk_iommu_domain_finalise()
395 dom->iop = data->m4u_dom->iop; in mtk_iommu_domain_finalise()
396 dom->cfg = data->m4u_dom->cfg; in mtk_iommu_domain_finalise()
397 dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap; in mtk_iommu_domain_finalise()
401 dom->cfg = (struct io_pgtable_cfg) { in mtk_iommu_domain_finalise()
406 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, in mtk_iommu_domain_finalise()
407 .iommu_dev = data->dev, in mtk_iommu_domain_finalise()
410 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) in mtk_iommu_domain_finalise()
411 dom->cfg.oas = data->enable_4GB ? 33 : 32; in mtk_iommu_domain_finalise()
413 dom->cfg.oas = 35; in mtk_iommu_domain_finalise()
415 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); in mtk_iommu_domain_finalise()
416 if (!dom->iop) { in mtk_iommu_domain_finalise()
417 dev_err(data->dev, "Failed to alloc io pgtable\n"); in mtk_iommu_domain_finalise()
418 return -EINVAL; in mtk_iommu_domain_finalise()
422 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; in mtk_iommu_domain_finalise()
426 region = data->plat_data->iova_region + domid; in mtk_iommu_domain_finalise()
427 dom->domain.geometry.aperture_start = region->iova_base; in mtk_iommu_domain_finalise()
428 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; in mtk_iommu_domain_finalise()
429 dom->domain.geometry.force_aperture = true; in mtk_iommu_domain_finalise()
444 if (iommu_get_dma_cookie(&dom->domain)) { in mtk_iommu_domain_alloc()
449 return &dom->domain; in mtk_iommu_domain_alloc()
463 struct device *m4udev = data->dev; in mtk_iommu_attach_device()
466 domid = mtk_iommu_get_domain_id(dev, data->plat_data); in mtk_iommu_attach_device()
470 if (!dom->data) { in mtk_iommu_attach_device()
475 return -ENODEV; in mtk_iommu_attach_device()
476 dom->data = data; in mtk_iommu_attach_device()
479 mutex_lock(&data->mutex); in mtk_iommu_attach_device()
480 if (!data->m4u_dom) { /* Initialize the M4U HW */ in mtk_iommu_attach_device()
490 data->m4u_dom = dom; in mtk_iommu_attach_device()
491 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, in mtk_iommu_attach_device()
492 data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_attach_device()
496 mutex_unlock(&data->mutex); in mtk_iommu_attach_device()
502 mutex_unlock(&data->mutex); in mtk_iommu_attach_device()
520 if (dom->data->enable_4GB) in mtk_iommu_map()
524 return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); in mtk_iommu_map()
532 unsigned long end = iova + size - 1; in mtk_iommu_unmap()
534 if (gather->start > iova) in mtk_iommu_unmap()
535 gather->start = iova; in mtk_iommu_unmap()
536 if (gather->end < end) in mtk_iommu_unmap()
537 gather->end = end; in mtk_iommu_unmap()
538 return dom->iop->unmap(dom->iop, iova, size, gather); in mtk_iommu_unmap()
545 mtk_iommu_tlb_flush_all(dom->data); in mtk_iommu_flush_iotlb_all()
552 size_t length = gather->end - gather->start + 1; in mtk_iommu_iotlb_sync()
554 mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, in mtk_iommu_iotlb_sync()
555 dom->data); in mtk_iommu_iotlb_sync()
563 mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data); in mtk_iommu_sync_map()
572 pa = dom->iop->iova_to_phys(dom->iop, iova); in mtk_iommu_iova_to_phys()
573 if (dom->data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) in mtk_iommu_iova_to_phys()
584 if (!fwspec || fwspec->ops != &mtk_iommu_ops) in mtk_iommu_probe_device()
585 return ERR_PTR(-ENODEV); /* Not a iommu client device */ in mtk_iommu_probe_device()
589 return &data->iommu; in mtk_iommu_probe_device()
596 if (!fwspec || fwspec->ops != &mtk_iommu_ops) in mtk_iommu_release_device()
609 return ERR_PTR(-ENODEV); in mtk_iommu_device_group()
611 domid = mtk_iommu_get_domain_id(dev, data->plat_data); in mtk_iommu_device_group()
615 mutex_lock(&data->mutex); in mtk_iommu_device_group()
616 group = data->m4u_group[domid]; in mtk_iommu_device_group()
620 data->m4u_group[domid] = group; in mtk_iommu_device_group()
624 mutex_unlock(&data->mutex); in mtk_iommu_device_group()
632 if (args->args_count != 1) { in mtk_iommu_of_xlate()
633 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", in mtk_iommu_of_xlate()
634 args->args_count); in mtk_iommu_of_xlate()
635 return -EINVAL; in mtk_iommu_of_xlate()
640 m4updev = of_find_device_by_node(args->np); in mtk_iommu_of_xlate()
642 return -EINVAL; in mtk_iommu_of_xlate()
647 return iommu_fwspec_add_ids(dev, args->args, 1); in mtk_iommu_of_xlate()
654 unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i; in mtk_iommu_get_resv_regions()
661 curdom = data->plat_data->iova_region + domid; in mtk_iommu_get_resv_regions()
662 for (i = 0; i < data->plat_data->iova_region_nr; i++) { in mtk_iommu_get_resv_regions()
663 resv = data->plat_data->iova_region + i; in mtk_iommu_get_resv_regions()
666 if (resv->iova_base <= curdom->iova_base || in mtk_iommu_get_resv_regions()
667 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) in mtk_iommu_get_resv_regions()
670 region = iommu_alloc_resv_region(resv->iova_base, resv->size, in mtk_iommu_get_resv_regions()
675 list_add_tail(®ion->list, head); in mtk_iommu_get_resv_regions()
703 if (data->plat_data->m4u_plat == M4U_MT8173) { in mtk_iommu_hw_init()
707 regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
710 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
718 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); in mtk_iommu_hw_init()
727 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_hw_init()
729 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) in mtk_iommu_hw_init()
730 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); in mtk_iommu_hw_init()
732 regval = lower_32_bits(data->protect_base) | in mtk_iommu_hw_init()
733 upper_32_bits(data->protect_base); in mtk_iommu_hw_init()
734 writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); in mtk_iommu_hw_init()
736 if (data->enable_4GB && in mtk_iommu_hw_init()
737 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { in mtk_iommu_hw_init()
743 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); in mtk_iommu_hw_init()
745 writel_relaxed(0, data->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
746 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { in mtk_iommu_hw_init()
748 regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
750 writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
753 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { in mtk_iommu_hw_init()
757 regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
759 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) in mtk_iommu_hw_init()
762 writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
764 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, in mtk_iommu_hw_init()
765 dev_name(data->dev), (void *)data)) { in mtk_iommu_hw_init()
766 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_hw_init()
767 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); in mtk_iommu_hw_init()
768 return -ENODEV; in mtk_iommu_hw_init()
782 struct device *dev = &pdev->dev; in mtk_iommu_probe()
797 return -ENOMEM; in mtk_iommu_probe()
798 data->dev = dev; in mtk_iommu_probe()
799 data->plat_data = of_device_get_match_data(dev); in mtk_iommu_probe()
804 return -ENOMEM; in mtk_iommu_probe()
805 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); in mtk_iommu_probe()
807 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { in mtk_iommu_probe()
808 switch (data->plat_data->m4u_plat) { in mtk_iommu_probe()
810 p = "mediatek,mt2712-infracfg"; in mtk_iommu_probe()
813 p = "mediatek,mt8173-infracfg"; in mtk_iommu_probe()
827 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); in mtk_iommu_probe()
831 data->base = devm_ioremap_resource(dev, res); in mtk_iommu_probe()
832 if (IS_ERR(data->base)) in mtk_iommu_probe()
833 return PTR_ERR(data->base); in mtk_iommu_probe()
834 ioaddr = res->start; in mtk_iommu_probe()
836 data->irq = platform_get_irq(pdev, 0); in mtk_iommu_probe()
837 if (data->irq < 0) in mtk_iommu_probe()
838 return data->irq; in mtk_iommu_probe()
840 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { in mtk_iommu_probe()
841 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_probe()
842 if (IS_ERR(data->bclk)) in mtk_iommu_probe()
843 return PTR_ERR(data->bclk); in mtk_iommu_probe()
846 larb_nr = of_count_phandle_with_args(dev->of_node, in mtk_iommu_probe()
854 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); in mtk_iommu_probe()
856 return -EINVAL; in mtk_iommu_probe()
863 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); in mtk_iommu_probe()
870 return -EPROBE_DEFER; in mtk_iommu_probe()
872 data->larb_imu[id].dev = &plarbdev->dev; in mtk_iommu_probe()
878 /* Get smi-common dev from the last larb. */ in mtk_iommu_probe()
879 smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); in mtk_iommu_probe()
881 return -EINVAL; in mtk_iommu_probe()
885 data->smicomm_dev = &plarbdev->dev; in mtk_iommu_probe()
889 link = device_link_add(data->smicomm_dev, dev, in mtk_iommu_probe()
892 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); in mtk_iommu_probe()
893 ret = -EINVAL; in mtk_iommu_probe()
898 mutex_init(&data->mutex); in mtk_iommu_probe()
900 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, in mtk_iommu_probe()
901 "mtk-iommu.%pa", &ioaddr); in mtk_iommu_probe()
905 iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); in mtk_iommu_probe()
906 iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); in mtk_iommu_probe()
908 ret = iommu_device_register(&data->iommu); in mtk_iommu_probe()
912 spin_lock_init(&data->tlb_lock); in mtk_iommu_probe()
913 list_add_tail(&data->list, &m4ulist); in mtk_iommu_probe()
929 list_del(&data->list); in mtk_iommu_probe()
930 iommu_device_unregister(&data->iommu); in mtk_iommu_probe()
932 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_probe()
934 device_link_remove(data->smicomm_dev, dev); in mtk_iommu_probe()
944 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_remove()
945 iommu_device_unregister(&data->iommu); in mtk_iommu_remove()
947 list_del(&data->list); in mtk_iommu_remove()
949 device_link_remove(data->smicomm_dev, &pdev->dev); in mtk_iommu_remove()
950 pm_runtime_disable(&pdev->dev); in mtk_iommu_remove()
951 devm_free_irq(&pdev->dev, data->irq, data); in mtk_iommu_remove()
952 component_master_del(&pdev->dev, &mtk_iommu_com_ops); in mtk_iommu_remove()
959 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_runtime_suspend()
960 void __iomem *base = data->base; in mtk_iommu_runtime_suspend()
962 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_runtime_suspend()
963 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); in mtk_iommu_runtime_suspend()
964 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); in mtk_iommu_runtime_suspend()
965 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); in mtk_iommu_runtime_suspend()
966 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); in mtk_iommu_runtime_suspend()
967 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_runtime_suspend()
968 reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); in mtk_iommu_runtime_suspend()
969 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); in mtk_iommu_runtime_suspend()
970 clk_disable_unprepare(data->bclk); in mtk_iommu_runtime_suspend()
977 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_runtime_resume()
978 struct mtk_iommu_domain *m4u_dom = data->m4u_dom; in mtk_iommu_runtime_resume()
979 void __iomem *base = data->base; in mtk_iommu_runtime_resume()
982 ret = clk_prepare_enable(data->bclk); in mtk_iommu_runtime_resume()
984 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); in mtk_iommu_runtime_resume()
995 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_runtime_resume()
996 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); in mtk_iommu_runtime_resume()
997 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); in mtk_iommu_runtime_resume()
998 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); in mtk_iommu_runtime_resume()
999 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); in mtk_iommu_runtime_resume()
1000 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_runtime_resume()
1001 writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); in mtk_iommu_runtime_resume()
1002 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); in mtk_iommu_runtime_resume()
1003 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_runtime_resume()
1071 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1072 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1073 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1074 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1075 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1076 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1084 .name = "mtk-iommu",