Lines Matching full:iommu
22 #include <linux/intel-iommu.h>
29 #include <linux/iommu.h>
65 static void free_iommu(struct intel_iommu *iommu);
462 if (dmaru->iommu) in dmar_free_drhd()
463 free_iommu(dmaru->iommu); in dmar_free_drhd()
502 drhd->iommu->node = node; in dmar_parse_one_rhsa()
761 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
933 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
948 static void unmap_iommu(struct intel_iommu *iommu) in unmap_iommu() argument
950 iounmap(iommu->reg); in unmap_iommu()
951 release_mem_region(iommu->reg_phys, iommu->reg_size); in unmap_iommu()
955 * map_iommu: map the iommu's registers
956 * @iommu: the iommu to map
959 * Memory map the iommu's registers. Start w/ a single page, and
962 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) in map_iommu() argument
966 iommu->reg_phys = phys_addr; in map_iommu()
967 iommu->reg_size = VTD_PAGE_SIZE; in map_iommu()
969 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { in map_iommu()
975 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
976 if (!iommu->reg) { in map_iommu()
982 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); in map_iommu()
983 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); in map_iommu()
985 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { in map_iommu()
990 if (ecap_vcs(iommu->ecap)) in map_iommu()
991 iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG); in map_iommu()
994 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), in map_iommu()
995 cap_max_fault_reg_offset(iommu->cap)); in map_iommu()
997 if (map_size > iommu->reg_size) { in map_iommu()
998 iounmap(iommu->reg); in map_iommu()
999 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1000 iommu->reg_size = map_size; in map_iommu()
1001 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, in map_iommu()
1002 iommu->name)) { in map_iommu()
1007 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
1008 if (!iommu->reg) { in map_iommu()
1018 iounmap(iommu->reg); in map_iommu()
1020 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1025 static int dmar_alloc_seq_id(struct intel_iommu *iommu) in dmar_alloc_seq_id() argument
1027 iommu->seq_id = find_first_zero_bit(dmar_seq_ids, in dmar_alloc_seq_id()
1029 if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) { in dmar_alloc_seq_id()
1030 iommu->seq_id = -1; in dmar_alloc_seq_id()
1032 set_bit(iommu->seq_id, dmar_seq_ids); in dmar_alloc_seq_id()
1033 sprintf(iommu->name, "dmar%d", iommu->seq_id); in dmar_alloc_seq_id()
1036 return iommu->seq_id; in dmar_alloc_seq_id()
1039 static void dmar_free_seq_id(struct intel_iommu *iommu) in dmar_free_seq_id() argument
1041 if (iommu->seq_id >= 0) { in dmar_free_seq_id()
1042 clear_bit(iommu->seq_id, dmar_seq_ids); in dmar_free_seq_id()
1043 iommu->seq_id = -1; in dmar_free_seq_id()
1049 struct intel_iommu *iommu; in alloc_iommu() local
1060 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); in alloc_iommu()
1061 if (!iommu) in alloc_iommu()
1064 if (dmar_alloc_seq_id(iommu) < 0) { in alloc_iommu()
1070 err = map_iommu(iommu, drhd->reg_base_addr); in alloc_iommu()
1072 pr_err("Failed to map %s\n", iommu->name); in alloc_iommu()
1077 if (cap_sagaw(iommu->cap) == 0) { in alloc_iommu()
1079 iommu->name); in alloc_iommu()
1084 agaw = iommu_calculate_agaw(iommu); in alloc_iommu()
1086 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", in alloc_iommu()
1087 iommu->seq_id); in alloc_iommu()
1092 msagaw = iommu_calculate_max_sagaw(iommu); in alloc_iommu()
1094 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", in alloc_iommu()
1095 iommu->seq_id); in alloc_iommu()
1100 iommu->agaw = agaw; in alloc_iommu()
1101 iommu->msagaw = msagaw; in alloc_iommu()
1102 iommu->segment = drhd->segment; in alloc_iommu()
1104 iommu->node = NUMA_NO_NODE; in alloc_iommu()
1106 ver = readl(iommu->reg + DMAR_VER_REG); in alloc_iommu()
1108 iommu->name, in alloc_iommu()
1111 (unsigned long long)iommu->cap, in alloc_iommu()
1112 (unsigned long long)iommu->ecap); in alloc_iommu()
1115 sts = readl(iommu->reg + DMAR_GSTS_REG); in alloc_iommu()
1117 iommu->gcmd |= DMA_GCMD_IRE; in alloc_iommu()
1119 iommu->gcmd |= DMA_GCMD_TE; in alloc_iommu()
1121 iommu->gcmd |= DMA_GCMD_QIE; in alloc_iommu()
1123 raw_spin_lock_init(&iommu->register_lock); in alloc_iommu()
1131 err = iommu_device_sysfs_add(&iommu->iommu, NULL, in alloc_iommu()
1133 "%s", iommu->name); in alloc_iommu()
1137 iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops); in alloc_iommu()
1139 err = iommu_device_register(&iommu->iommu); in alloc_iommu()
1144 drhd->iommu = iommu; in alloc_iommu()
1145 iommu->drhd = drhd; in alloc_iommu()
1150 iommu_device_sysfs_remove(&iommu->iommu); in alloc_iommu()
1152 unmap_iommu(iommu); in alloc_iommu()
1154 dmar_free_seq_id(iommu); in alloc_iommu()
1156 kfree(iommu); in alloc_iommu()
1160 static void free_iommu(struct intel_iommu *iommu) in free_iommu() argument
1162 if (intel_iommu_enabled && !iommu->drhd->ignored) { in free_iommu()
1163 iommu_device_unregister(&iommu->iommu); in free_iommu()
1164 iommu_device_sysfs_remove(&iommu->iommu); in free_iommu()
1167 if (iommu->irq) { in free_iommu()
1168 if (iommu->pr_irq) { in free_iommu()
1169 free_irq(iommu->pr_irq, iommu); in free_iommu()
1170 dmar_free_hwirq(iommu->pr_irq); in free_iommu()
1171 iommu->pr_irq = 0; in free_iommu()
1173 free_irq(iommu->irq, iommu); in free_iommu()
1174 dmar_free_hwirq(iommu->irq); in free_iommu()
1175 iommu->irq = 0; in free_iommu()
1178 if (iommu->qi) { in free_iommu()
1179 free_page((unsigned long)iommu->qi->desc); in free_iommu()
1180 kfree(iommu->qi->desc_status); in free_iommu()
1181 kfree(iommu->qi); in free_iommu()
1184 if (iommu->reg) in free_iommu()
1185 unmap_iommu(iommu); in free_iommu()
1187 dmar_free_seq_id(iommu); in free_iommu()
1188 kfree(iommu); in free_iommu()
1204 static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index) in qi_check_fault() argument
1208 struct q_inval *qi = iommu->qi; in qi_check_fault()
1209 int shift = qi_shift(iommu); in qi_check_fault()
1214 fault = readl(iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1222 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1236 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1246 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1249 tail = readl(iommu->reg + DMAR_IQT_REG); in qi_check_fault()
1252 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1265 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1277 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, in qi_submit_sync() argument
1280 struct q_inval *qi = iommu->qi; in qi_submit_sync()
1307 shift = qi_shift(iommu); in qi_submit_sync()
1334 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); in qi_submit_sync()
1344 rc = qi_check_fault(iommu, index, wait_index); in qi_submit_sync()
1368 void qi_global_iec(struct intel_iommu *iommu) in qi_global_iec() argument
1378 qi_submit_sync(iommu, &desc, 1, 0); in qi_global_iec()
1381 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, in qi_flush_context() argument
1392 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_context()
1395 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, in qi_flush_iotlb() argument
1403 if (cap_write_drain(iommu->cap)) in qi_flush_iotlb()
1406 if (cap_read_drain(iommu->cap)) in qi_flush_iotlb()
1416 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_iotlb()
1419 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, in qi_flush_dev_iotlb() argument
1438 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_dev_iotlb()
1442 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, in qi_flush_piotlb() argument
1479 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_piotlb()
1483 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, in qi_flush_dev_iotlb_pasid() argument
1523 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_dev_iotlb_pasid()
1526 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, in qi_flush_pasid_cache() argument
1533 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_pasid_cache()
1539 void dmar_disable_qi(struct intel_iommu *iommu) in dmar_disable_qi() argument
1545 if (!ecap_qis(iommu->ecap)) in dmar_disable_qi()
1548 raw_spin_lock_irqsave(&iommu->register_lock, flags); in dmar_disable_qi()
1550 sts = readl(iommu->reg + DMAR_GSTS_REG); in dmar_disable_qi()
1557 while ((readl(iommu->reg + DMAR_IQT_REG) != in dmar_disable_qi()
1558 readl(iommu->reg + DMAR_IQH_REG)) && in dmar_disable_qi()
1562 iommu->gcmd &= ~DMA_GCMD_QIE; in dmar_disable_qi()
1563 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in dmar_disable_qi()
1565 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, in dmar_disable_qi()
1568 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in dmar_disable_qi()
1574 static void __dmar_enable_qi(struct intel_iommu *iommu) in __dmar_enable_qi() argument
1578 struct q_inval *qi = iommu->qi; in __dmar_enable_qi()
1588 if (ecap_smts(iommu->ecap)) in __dmar_enable_qi()
1591 raw_spin_lock_irqsave(&iommu->register_lock, flags); in __dmar_enable_qi()
1594 writel(0, iommu->reg + DMAR_IQT_REG); in __dmar_enable_qi()
1596 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); in __dmar_enable_qi()
1598 iommu->gcmd |= DMA_GCMD_QIE; in __dmar_enable_qi()
1599 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in __dmar_enable_qi()
1602 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); in __dmar_enable_qi()
1604 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in __dmar_enable_qi()
1612 int dmar_enable_qi(struct intel_iommu *iommu) in dmar_enable_qi() argument
1617 if (!ecap_qis(iommu->ecap)) in dmar_enable_qi()
1623 if (iommu->qi) in dmar_enable_qi()
1626 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); in dmar_enable_qi()
1627 if (!iommu->qi) in dmar_enable_qi()
1630 qi = iommu->qi; in dmar_enable_qi()
1636 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, in dmar_enable_qi()
1637 !!ecap_smts(iommu->ecap)); in dmar_enable_qi()
1640 iommu->qi = NULL; in dmar_enable_qi()
1650 iommu->qi = NULL; in dmar_enable_qi()
1656 __dmar_enable_qi(iommu); in dmar_enable_qi()
1661 /* iommu interrupt handling. Most stuff are MSI-like. */
1776 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq) in dmar_msi_reg() argument
1778 if (iommu->irq == irq) in dmar_msi_reg()
1780 else if (iommu->pr_irq == irq) in dmar_msi_reg()
1788 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); in dmar_msi_unmask() local
1789 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_unmask()
1793 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_unmask()
1794 writel(0, iommu->reg + reg); in dmar_msi_unmask()
1796 readl(iommu->reg + reg); in dmar_msi_unmask()
1797 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_unmask()
1802 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); in dmar_msi_mask() local
1803 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_mask()
1807 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_mask()
1808 writel(DMA_FECTL_IM, iommu->reg + reg); in dmar_msi_mask()
1810 readl(iommu->reg + reg); in dmar_msi_mask()
1811 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_mask()
1816 struct intel_iommu *iommu = irq_get_handler_data(irq); in dmar_msi_write() local
1817 int reg = dmar_msi_reg(iommu, irq); in dmar_msi_write()
1820 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_write()
1821 writel(msg->data, iommu->reg + reg + 4); in dmar_msi_write()
1822 writel(msg->address_lo, iommu->reg + reg + 8); in dmar_msi_write()
1823 writel(msg->address_hi, iommu->reg + reg + 12); in dmar_msi_write()
1824 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_write()
1829 struct intel_iommu *iommu = irq_get_handler_data(irq); in dmar_msi_read() local
1830 int reg = dmar_msi_reg(iommu, irq); in dmar_msi_read()
1833 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_read()
1834 msg->data = readl(iommu->reg + reg + 4); in dmar_msi_read()
1835 msg->address_lo = readl(iommu->reg + reg + 8); in dmar_msi_read()
1836 msg->address_hi = readl(iommu->reg + reg + 12); in dmar_msi_read()
1837 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_read()
1840 static int dmar_fault_do_one(struct intel_iommu *iommu, int type, in dmar_fault_do_one() argument
1866 struct intel_iommu *iommu = dev_id; in dmar_fault() local
1874 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
1875 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in dmar_fault()
1884 reg = cap_fault_reg_offset(iommu->cap); in dmar_fault()
1897 data = readl(iommu->reg + reg + in dmar_fault()
1907 data = readl(iommu->reg + reg + in dmar_fault()
1912 guest_addr = dmar_readq(iommu->reg + reg + in dmar_fault()
1918 writel(DMA_FRCD_F, iommu->reg + reg + in dmar_fault()
1921 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
1925 dmar_fault_do_one(iommu, type, fault_reason, in dmar_fault()
1930 if (fault_index >= cap_num_fault_regs(iommu->cap)) in dmar_fault()
1932 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
1936 iommu->reg + DMAR_FSTS_REG); in dmar_fault()
1939 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
1943 int dmar_set_interrupt(struct intel_iommu *iommu) in dmar_set_interrupt() argument
1950 if (iommu->irq) in dmar_set_interrupt()
1953 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); in dmar_set_interrupt()
1955 iommu->irq = irq; in dmar_set_interrupt()
1961 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); in dmar_set_interrupt()
1970 struct intel_iommu *iommu; in enable_drhd_fault_handling() local
1975 for_each_iommu(iommu, drhd) { in enable_drhd_fault_handling()
1977 int ret = dmar_set_interrupt(iommu); in enable_drhd_fault_handling()
1988 dmar_fault(iommu->irq, iommu); in enable_drhd_fault_handling()
1989 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
1990 writel(fault_status, iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
1999 int dmar_reenable_qi(struct intel_iommu *iommu) in dmar_reenable_qi() argument
2001 if (!ecap_qis(iommu->ecap)) in dmar_reenable_qi()
2004 if (!iommu->qi) in dmar_reenable_qi()
2010 dmar_disable_qi(iommu); in dmar_reenable_qi()
2016 __dmar_enable_qi(iommu); in dmar_reenable_qi()