251 	__arm_smmu_tlb_sync(smmu, ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx),  in arm_smmu_tlb_sync_context()
264 	arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx,  in arm_smmu_tlb_inv_context_s1()
286 	int idx = cfg->cbndx;  in arm_smmu_tlb_inv_range_s1()
313 	int idx = smmu_domain->cfg.cbndx;  in arm_smmu_tlb_inv_range_s2()
410 	int idx = smmu_domain->cfg.cbndx;  in arm_smmu_context_fault()
465 	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];  in arm_smmu_init_context_bank()
739 	cfg->cbndx = ret;  in arm_smmu_init_domain_context()
744 		cfg->irptndx = cfg->cbndx;  in arm_smmu_init_domain_context()
748 		cfg->vmid = cfg->cbndx + 1;  in arm_smmu_init_domain_context()
750 		cfg->asid = cfg->cbndx;  in arm_smmu_init_domain_context()
790 	arm_smmu_write_context_bank(smmu, cfg->cbndx);  in arm_smmu_init_domain_context()
818 	__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);  in arm_smmu_init_domain_context()
843 	smmu->cbs[cfg->cbndx].cfg = NULL;  in arm_smmu_destroy_domain_context()
844 	arm_smmu_write_context_bank(smmu, cfg->cbndx);  in arm_smmu_destroy_domain_context()
852 	__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);  in arm_smmu_destroy_domain_context()
921 	      FIELD_PREP(ARM_SMMU_S2CR_CBNDX, s2cr->cbndx) |  in arm_smmu_write_s2cr()
1022 	u8 cbndx = smmu->s2crs[idx].cbndx;  in arm_smmu_free_sme()  local
1030 		smmu->s2crs[idx].cbndx = cbndx;  in arm_smmu_free_sme()
1108 	u8 cbndx = smmu_domain->cfg.cbndx;  in arm_smmu_domain_add_master()  local
1118 		if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx)  in arm_smmu_domain_add_master()
1127 		s2cr[idx].cbndx = cbndx;  in arm_smmu_domain_add_master()
1280 	int ret, idx = cfg->cbndx;  in arm_smmu_iova_to_phys_hard()