Lines Matching +full:smmu +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for ARM architected SMMU implementations.
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-iommu.h>
25 #include <linux/dma-mapping.h>
44 #include "arm-smmu.h"
47 * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU
53 #define QCOM_DUMMY_VAL -1
61 …"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' f…
66 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
74 static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu) in arm_smmu_rpm_get() argument
76 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_get()
77 return pm_runtime_resume_and_get(smmu->dev); in arm_smmu_rpm_get()
82 static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu) in arm_smmu_rpm_put() argument
84 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_put()
85 pm_runtime_put_autosuspend(smmu->dev); in arm_smmu_rpm_put()
102 struct pci_bus *bus = to_pci_dev(dev)->bus; in dev_get_dev_node()
105 bus = bus->parent; in dev_get_dev_node()
106 return of_node_get(bus->bridge->parent->of_node); in dev_get_dev_node()
109 return of_node_get(dev->of_node); in dev_get_dev_node()
121 struct device_node *np = it->node; in __find_legacy_master_phandle()
124 of_for_each_phandle(it, err, dev->of_node, "mmu-masters", in __find_legacy_master_phandle()
125 "#stream-id-cells", -1) in __find_legacy_master_phandle()
126 if (it->node == np) { in __find_legacy_master_phandle()
130 it->node = np; in __find_legacy_master_phandle()
131 return err == -ENOENT ? 0 : err; in __find_legacy_master_phandle()
135 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
146 if (!np || !of_find_property(np, "#stream-id-cells", NULL)) { in arm_smmu_register_legacy_master()
148 return -ENODEV; in arm_smmu_register_legacy_master()
157 return -ENODEV; in arm_smmu_register_legacy_master()
162 /* "mmu-masters" assumes Stream ID == Requester ID */ in arm_smmu_register_legacy_master()
169 err = iommu_fwspec_init(dev, &smmu_dev->of_node->fwnode, in arm_smmu_register_legacy_master()
176 return -ENOMEM; in arm_smmu_register_legacy_master()
178 *smmu = dev_get_drvdata(smmu_dev); in arm_smmu_register_legacy_master()
188 * delay setting bus ops until we're sure every possible SMMU is ready,
200 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
202 return -ENODEV; in arm_smmu_register_legacy_master()
212 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in __arm_smmu_tlb_sync() argument
218 if (smmu->impl && unlikely(smmu->impl->tlb_sync)) in __arm_smmu_tlb_sync()
219 return smmu->impl->tlb_sync(smmu, page, sync, status); in __arm_smmu_tlb_sync()
221 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in __arm_smmu_tlb_sync()
223 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in __arm_smmu_tlb_sync()
224 reg = arm_smmu_readl(smmu, page, status); in __arm_smmu_tlb_sync()
231 dev_err_ratelimited(smmu->dev, in __arm_smmu_tlb_sync()
232 "TLB sync timed out -- SMMU may be deadlocked\n"); in __arm_smmu_tlb_sync()
235 static void arm_smmu_tlb_sync_global(struct arm_smmu_device *smmu) in arm_smmu_tlb_sync_global() argument
239 spin_lock_irqsave(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
240 __arm_smmu_tlb_sync(smmu, ARM_SMMU_GR0, ARM_SMMU_GR0_sTLBGSYNC, in arm_smmu_tlb_sync_global()
242 spin_unlock_irqrestore(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
247 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_sync_context() local
250 spin_lock_irqsave(&smmu_domain->cb_lock, flags); in arm_smmu_tlb_sync_context()
251 __arm_smmu_tlb_sync(smmu, ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx), in arm_smmu_tlb_sync_context()
253 spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); in arm_smmu_tlb_sync_context()
264 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
265 ARM_SMMU_CB_S1_TLBIASID, smmu_domain->cfg.asid); in arm_smmu_tlb_inv_context_s1()
272 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context_s2() local
276 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_inv_context_s2()
277 arm_smmu_tlb_sync_global(smmu); in arm_smmu_tlb_inv_context_s2()
284 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s1() local
285 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_tlb_inv_range_s1()
286 int idx = cfg->cbndx; in arm_smmu_tlb_inv_range_s1()
288 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s1()
291 if (cfg->fmt != ARM_SMMU_CTX_FMT_AARCH64) { in arm_smmu_tlb_inv_range_s1()
293 iova |= cfg->asid; in arm_smmu_tlb_inv_range_s1()
295 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
297 } while (size -= granule); in arm_smmu_tlb_inv_range_s1()
300 iova |= (u64)cfg->asid << 48; in arm_smmu_tlb_inv_range_s1()
302 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
304 } while (size -= granule); in arm_smmu_tlb_inv_range_s1()
312 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s2() local
313 int idx = smmu_domain->cfg.cbndx; in arm_smmu_tlb_inv_range_s2()
315 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s2()
320 if (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64) in arm_smmu_tlb_inv_range_s2()
321 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
323 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
325 } while (size -= granule); in arm_smmu_tlb_inv_range_s2()
366 * On MMU-401 at least, the cost of firing off multiple TLBIVMIDs appears
369 * no-op and call arm_smmu_tlb_inv_context_s2() from .iotlb_sync as you might
377 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_add_page_s2_v1() local
379 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_add_page_s2_v1()
382 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_add_page_s2_v1()
409 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_context_fault() local
410 int idx = smmu_domain->cfg.cbndx; in arm_smmu_context_fault()
412 fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); in arm_smmu_context_fault()
416 fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); in arm_smmu_context_fault()
417 iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); in arm_smmu_context_fault()
418 cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); in arm_smmu_context_fault()
420 dev_err_ratelimited(smmu->dev, in arm_smmu_context_fault()
424 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); in arm_smmu_context_fault()
431 struct arm_smmu_device *smmu = dev; in arm_smmu_global_fault() local
435 gfsr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_global_fault()
436 gfsynr0 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR0); in arm_smmu_global_fault()
437 gfsynr1 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR1); in arm_smmu_global_fault()
438 gfsynr2 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR2); in arm_smmu_global_fault()
446 dev_err(smmu->dev, in arm_smmu_global_fault()
447 …"Blocked unknown Stream ID 0x%hx; boot with \"arm-smmu.disable_bypass=0\" to allow, but this may h… in arm_smmu_global_fault()
450 dev_err(smmu->dev, in arm_smmu_global_fault()
452 dev_err(smmu->dev, in arm_smmu_global_fault()
457 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr); in arm_smmu_global_fault()
464 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_init_context_bank()
465 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; in arm_smmu_init_context_bank()
466 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_init_context_bank()
468 cb->cfg = cfg; in arm_smmu_init_context_bank()
472 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { in arm_smmu_init_context_bank()
473 cb->tcr[0] = pgtbl_cfg->arm_v7s_cfg.tcr; in arm_smmu_init_context_bank()
475 cb->tcr[0] = arm_smmu_lpae_tcr(pgtbl_cfg); in arm_smmu_init_context_bank()
476 cb->tcr[1] = arm_smmu_lpae_tcr2(pgtbl_cfg); in arm_smmu_init_context_bank()
477 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) in arm_smmu_init_context_bank()
478 cb->tcr[1] |= ARM_SMMU_TCR2_AS; in arm_smmu_init_context_bank()
480 cb->tcr[0] |= ARM_SMMU_TCR_EAE; in arm_smmu_init_context_bank()
483 cb->tcr[0] = arm_smmu_lpae_vtcr(pgtbl_cfg); in arm_smmu_init_context_bank()
488 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { in arm_smmu_init_context_bank()
489 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; in arm_smmu_init_context_bank()
490 cb->ttbr[1] = 0; in arm_smmu_init_context_bank()
492 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
493 cfg->asid); in arm_smmu_init_context_bank()
494 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
495 cfg->asid); in arm_smmu_init_context_bank()
497 if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) in arm_smmu_init_context_bank()
498 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
500 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
503 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_init_context_bank()
506 /* MAIRs (stage-1 only) */ in arm_smmu_init_context_bank()
508 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { in arm_smmu_init_context_bank()
509 cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr; in arm_smmu_init_context_bank()
510 cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr; in arm_smmu_init_context_bank()
512 cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair; in arm_smmu_init_context_bank()
513 cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair >> 32; in arm_smmu_init_context_bank()
518 void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_context_bank() argument
522 struct arm_smmu_cb *cb = &smmu->cbs[idx]; in arm_smmu_write_context_bank()
523 struct arm_smmu_cfg *cfg = cb->cfg; in arm_smmu_write_context_bank()
527 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, 0); in arm_smmu_write_context_bank()
531 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_write_context_bank()
534 if (smmu->version > ARM_SMMU_V1) { in arm_smmu_write_context_bank()
535 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) in arm_smmu_write_context_bank()
539 /* 16-bit VMIDs live in CBA2R */ in arm_smmu_write_context_bank()
540 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_write_context_bank()
541 reg |= FIELD_PREP(ARM_SMMU_CBA2R_VMID16, cfg->vmid); in arm_smmu_write_context_bank()
543 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBA2R(idx), reg); in arm_smmu_write_context_bank()
547 reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, cfg->cbar); in arm_smmu_write_context_bank()
548 if (smmu->version < ARM_SMMU_V2) in arm_smmu_write_context_bank()
549 reg |= FIELD_PREP(ARM_SMMU_CBAR_IRPTNDX, cfg->irptndx); in arm_smmu_write_context_bank()
560 } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) { in arm_smmu_write_context_bank()
561 /* 8-bit VMIDs live in CBAR */ in arm_smmu_write_context_bank()
562 reg |= FIELD_PREP(ARM_SMMU_CBAR_VMID, cfg->vmid); in arm_smmu_write_context_bank()
564 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(idx), reg); in arm_smmu_write_context_bank()
571 if (stage1 && smmu->version > ARM_SMMU_V1) in arm_smmu_write_context_bank()
572 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); in arm_smmu_write_context_bank()
573 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); in arm_smmu_write_context_bank()
576 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_S) { in arm_smmu_write_context_bank()
577 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_CONTEXTIDR, cfg->asid); in arm_smmu_write_context_bank()
578 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
579 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
581 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
583 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR1, in arm_smmu_write_context_bank()
584 cb->ttbr[1]); in arm_smmu_write_context_bank()
587 /* MAIRs (stage-1 only) */ in arm_smmu_write_context_bank()
589 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR0, cb->mair[0]); in arm_smmu_write_context_bank()
590 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR1, cb->mair[1]); in arm_smmu_write_context_bank()
601 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in arm_smmu_write_context_bank()
605 struct arm_smmu_device *smmu, in arm_smmu_alloc_context_bank() argument
608 if (smmu->impl && smmu->impl->alloc_context_bank) in arm_smmu_alloc_context_bank()
609 return smmu->impl->alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_alloc_context_bank()
611 return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); in arm_smmu_alloc_context_bank()
615 struct arm_smmu_device *smmu, in arm_smmu_init_domain_context() argument
624 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_init_domain_context()
627 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_init_domain_context()
628 if (smmu_domain->smmu) in arm_smmu_init_domain_context()
631 if (domain->type == IOMMU_DOMAIN_IDENTITY) { in arm_smmu_init_domain_context()
632 smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; in arm_smmu_init_domain_context()
633 smmu_domain->smmu = smmu; in arm_smmu_init_domain_context()
653 * Note that you can't actually request stage-2 mappings. in arm_smmu_init_domain_context()
655 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_init_domain_context()
656 smmu_domain->stage = ARM_SMMU_DOMAIN_S2; in arm_smmu_init_domain_context()
657 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_init_domain_context()
658 smmu_domain->stage = ARM_SMMU_DOMAIN_S1; in arm_smmu_init_domain_context()
663 * the decision into the io-pgtable code where it arguably belongs, in arm_smmu_init_domain_context()
668 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) in arm_smmu_init_domain_context()
669 cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_L; in arm_smmu_init_domain_context()
672 (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && in arm_smmu_init_domain_context()
673 (smmu_domain->stage == ARM_SMMU_DOMAIN_S1)) in arm_smmu_init_domain_context()
674 cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_S; in arm_smmu_init_domain_context()
675 if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) && in arm_smmu_init_domain_context()
676 (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | in arm_smmu_init_domain_context()
679 cfg->fmt = ARM_SMMU_CTX_FMT_AARCH64; in arm_smmu_init_domain_context()
681 if (cfg->fmt == ARM_SMMU_CTX_FMT_NONE) { in arm_smmu_init_domain_context()
682 ret = -EINVAL; in arm_smmu_init_domain_context()
686 switch (smmu_domain->stage) { in arm_smmu_init_domain_context()
688 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; in arm_smmu_init_domain_context()
689 start = smmu->num_s2_context_banks; in arm_smmu_init_domain_context()
690 ias = smmu->va_size; in arm_smmu_init_domain_context()
691 oas = smmu->ipa_size; in arm_smmu_init_domain_context()
692 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) { in arm_smmu_init_domain_context()
694 } else if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH32_L) { in arm_smmu_init_domain_context()
703 smmu_domain->flush_ops = &arm_smmu_s1_tlb_ops; in arm_smmu_init_domain_context()
711 cfg->cbar = CBAR_TYPE_S2_TRANS; in arm_smmu_init_domain_context()
713 ias = smmu->ipa_size; in arm_smmu_init_domain_context()
714 oas = smmu->pa_size; in arm_smmu_init_domain_context()
715 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) { in arm_smmu_init_domain_context()
722 if (smmu->version == ARM_SMMU_V2) in arm_smmu_init_domain_context()
723 smmu_domain->flush_ops = &arm_smmu_s2_tlb_ops_v2; in arm_smmu_init_domain_context()
725 smmu_domain->flush_ops = &arm_smmu_s2_tlb_ops_v1; in arm_smmu_init_domain_context()
728 ret = -EINVAL; in arm_smmu_init_domain_context()
732 ret = arm_smmu_alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_init_domain_context()
737 smmu_domain->smmu = smmu; in arm_smmu_init_domain_context()
739 cfg->cbndx = ret; in arm_smmu_init_domain_context()
740 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_init_domain_context()
741 cfg->irptndx = atomic_inc_return(&smmu->irptndx); in arm_smmu_init_domain_context()
742 cfg->irptndx %= smmu->num_context_irqs; in arm_smmu_init_domain_context()
744 cfg->irptndx = cfg->cbndx; in arm_smmu_init_domain_context()
747 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in arm_smmu_init_domain_context()
748 cfg->vmid = cfg->cbndx + 1; in arm_smmu_init_domain_context()
750 cfg->asid = cfg->cbndx; in arm_smmu_init_domain_context()
753 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_init_domain_context()
756 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK, in arm_smmu_init_domain_context()
757 .tlb = smmu_domain->flush_ops, in arm_smmu_init_domain_context()
758 .iommu_dev = smmu->dev, in arm_smmu_init_domain_context()
761 if (smmu->impl && smmu->impl->init_context) { in arm_smmu_init_domain_context()
762 ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg, dev); in arm_smmu_init_domain_context()
767 if (smmu_domain->non_strict) in arm_smmu_init_domain_context()
772 ret = -ENOMEM; in arm_smmu_init_domain_context()
777 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; in arm_smmu_init_domain_context()
780 domain->geometry.aperture_start = ~0UL << ias; in arm_smmu_init_domain_context()
781 domain->geometry.aperture_end = ~0UL; in arm_smmu_init_domain_context()
783 domain->geometry.aperture_end = (1UL << ias) - 1; in arm_smmu_init_domain_context()
786 domain->geometry.force_aperture = true; in arm_smmu_init_domain_context()
790 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_init_domain_context()
794 * handler seeing a half-initialised domain state. in arm_smmu_init_domain_context()
796 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; in arm_smmu_init_domain_context()
798 if (smmu->impl && smmu->impl->context_fault) in arm_smmu_init_domain_context()
799 context_fault = smmu->impl->context_fault; in arm_smmu_init_domain_context()
803 ret = devm_request_irq(smmu->dev, irq, context_fault, in arm_smmu_init_domain_context()
804 IRQF_SHARED, "arm-smmu-context-fault", domain); in arm_smmu_init_domain_context()
806 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", in arm_smmu_init_domain_context()
807 cfg->irptndx, irq); in arm_smmu_init_domain_context()
808 cfg->irptndx = ARM_SMMU_INVALID_IRPTNDX; in arm_smmu_init_domain_context()
811 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_init_domain_context()
814 smmu_domain->pgtbl_ops = pgtbl_ops; in arm_smmu_init_domain_context()
818 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_init_domain_context()
819 smmu_domain->smmu = NULL; in arm_smmu_init_domain_context()
821 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_init_domain_context()
828 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_destroy_domain_context() local
829 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_destroy_domain_context()
832 if (!smmu || domain->type == IOMMU_DOMAIN_IDENTITY) in arm_smmu_destroy_domain_context()
835 ret = arm_smmu_rpm_get(smmu); in arm_smmu_destroy_domain_context()
843 smmu->cbs[cfg->cbndx].cfg = NULL; in arm_smmu_destroy_domain_context()
844 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_destroy_domain_context()
846 if (cfg->irptndx != ARM_SMMU_INVALID_IRPTNDX) { in arm_smmu_destroy_domain_context()
847 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; in arm_smmu_destroy_domain_context()
848 devm_free_irq(smmu->dev, irq, domain); in arm_smmu_destroy_domain_context()
851 free_io_pgtable_ops(smmu_domain->pgtbl_ops); in arm_smmu_destroy_domain_context()
852 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_destroy_domain_context()
854 arm_smmu_rpm_put(smmu); in arm_smmu_destroy_domain_context()
875 iommu_get_dma_cookie(&smmu_domain->domain))) { in arm_smmu_domain_alloc()
880 mutex_init(&smmu_domain->init_mutex); in arm_smmu_domain_alloc()
881 spin_lock_init(&smmu_domain->cb_lock); in arm_smmu_domain_alloc()
883 return &smmu_domain->domain; in arm_smmu_domain_alloc()
899 static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_smr() argument
901 struct arm_smmu_smr *smr = smmu->smrs + idx; in arm_smmu_write_smr()
902 u32 reg = FIELD_PREP(ARM_SMMU_SMR_ID, smr->id) | in arm_smmu_write_smr()
903 FIELD_PREP(ARM_SMMU_SMR_MASK, smr->mask); in arm_smmu_write_smr()
905 if (!(smmu->features & ARM_SMMU_FEAT_EXIDS) && smr->valid) in arm_smmu_write_smr()
907 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(idx), reg); in arm_smmu_write_smr()
910 static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_s2cr() argument
912 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; in arm_smmu_write_s2cr()
915 if (smmu->impl && smmu->impl->write_s2cr) { in arm_smmu_write_s2cr()
916 smmu->impl->write_s2cr(smmu, idx); in arm_smmu_write_s2cr()
920 reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, s2cr->type) | in arm_smmu_write_s2cr()
921 FIELD_PREP(ARM_SMMU_S2CR_CBNDX, s2cr->cbndx) | in arm_smmu_write_s2cr()
922 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); in arm_smmu_write_s2cr()
924 if (smmu->features & ARM_SMMU_FEAT_EXIDS && smmu->smrs && in arm_smmu_write_s2cr()
925 smmu->smrs[idx].valid) in arm_smmu_write_s2cr()
927 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); in arm_smmu_write_s2cr()
930 static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_sme() argument
932 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_write_sme()
933 if (smmu->smrs) in arm_smmu_write_sme()
934 arm_smmu_write_smr(smmu, idx); in arm_smmu_write_sme()
941 static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu) in arm_smmu_test_smr_masks() argument
946 if (!smmu->smrs) in arm_smmu_test_smr_masks()
956 for (i = 0; i < smmu->num_mapping_groups; i++) in arm_smmu_test_smr_masks()
957 if (!smmu->smrs[i].valid) in arm_smmu_test_smr_masks()
966 smr = FIELD_PREP(ARM_SMMU_SMR_ID, smmu->streamid_mask); in arm_smmu_test_smr_masks()
967 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
968 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
969 smmu->streamid_mask = FIELD_GET(ARM_SMMU_SMR_ID, smr); in arm_smmu_test_smr_masks()
971 smr = FIELD_PREP(ARM_SMMU_SMR_MASK, smmu->streamid_mask); in arm_smmu_test_smr_masks()
972 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
973 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
974 smmu->smr_mask_mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in arm_smmu_test_smr_masks()
977 static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) in arm_smmu_find_sme() argument
979 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_find_sme()
980 int i, free_idx = -ENOSPC; in arm_smmu_find_sme()
987 for (i = 0; i < smmu->num_mapping_groups; ++i) { in arm_smmu_find_sme()
1013 return -EINVAL; in arm_smmu_find_sme()
1019 static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_free_sme() argument
1021 bool pinned = smmu->s2crs[idx].pinned; in arm_smmu_free_sme()
1022 u8 cbndx = smmu->s2crs[idx].cbndx; in arm_smmu_free_sme()
1024 if (--smmu->s2crs[idx].count) in arm_smmu_free_sme()
1027 smmu->s2crs[idx] = s2cr_init_val; in arm_smmu_free_sme()
1029 smmu->s2crs[idx].pinned = true; in arm_smmu_free_sme()
1030 smmu->s2crs[idx].cbndx = cbndx; in arm_smmu_free_sme()
1031 } else if (smmu->smrs) { in arm_smmu_free_sme()
1032 smmu->smrs[idx].valid = false; in arm_smmu_free_sme()
1042 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_alloc_smes() local
1043 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_master_alloc_smes()
1046 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1049 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); in arm_smmu_master_alloc_smes()
1050 u16 mask = FIELD_GET(ARM_SMMU_SMR_MASK, fwspec->ids[i]); in arm_smmu_master_alloc_smes()
1053 ret = -EEXIST; in arm_smmu_master_alloc_smes()
1057 ret = arm_smmu_find_sme(smmu, sid, mask); in arm_smmu_master_alloc_smes()
1062 if (smrs && smmu->s2crs[idx].count == 0) { in arm_smmu_master_alloc_smes()
1067 smmu->s2crs[idx].count++; in arm_smmu_master_alloc_smes()
1068 cfg->smendx[i] = (s16)idx; in arm_smmu_master_alloc_smes()
1073 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_alloc_smes()
1075 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1079 while (i--) { in arm_smmu_master_alloc_smes()
1080 arm_smmu_free_sme(smmu, cfg->smendx[i]); in arm_smmu_master_alloc_smes()
1081 cfg->smendx[i] = INVALID_SMENDX; in arm_smmu_master_alloc_smes()
1083 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1090 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_free_smes() local
1093 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1095 if (arm_smmu_free_sme(smmu, idx)) in arm_smmu_master_free_smes()
1096 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_free_smes()
1097 cfg->smendx[i] = INVALID_SMENDX; in arm_smmu_master_free_smes()
1099 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1106 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_add_master() local
1107 struct arm_smmu_s2cr *s2cr = smmu->s2crs; in arm_smmu_domain_add_master()
1108 u8 cbndx = smmu_domain->cfg.cbndx; in arm_smmu_domain_add_master()
1112 if (smmu_domain->stage == ARM_SMMU_DOMAIN_BYPASS) in arm_smmu_domain_add_master()
1128 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_domain_add_master()
1138 struct arm_smmu_device *smmu; in arm_smmu_attach_dev() local
1141 if (!fwspec || fwspec->ops != &arm_smmu_ops) { in arm_smmu_attach_dev()
1142 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); in arm_smmu_attach_dev()
1143 return -ENXIO; in arm_smmu_attach_dev()
1148 * domains between of_xlate() and probe_device() - we have no way to cope in arm_smmu_attach_dev()
1155 return -ENODEV; in arm_smmu_attach_dev()
1157 smmu = cfg->smmu; in arm_smmu_attach_dev()
1159 ret = arm_smmu_rpm_get(smmu); in arm_smmu_attach_dev()
1164 ret = arm_smmu_init_domain_context(domain, smmu, dev); in arm_smmu_attach_dev()
1172 if (smmu_domain->smmu != smmu) { in arm_smmu_attach_dev()
1174 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", in arm_smmu_attach_dev()
1175 dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); in arm_smmu_attach_dev()
1176 ret = -EINVAL; in arm_smmu_attach_dev()
1191 * to 5-10sec worth of reprogramming the context bank, while in arm_smmu_attach_dev()
1194 pm_runtime_set_autosuspend_delay(smmu->dev, 20); in arm_smmu_attach_dev()
1195 pm_runtime_use_autosuspend(smmu->dev); in arm_smmu_attach_dev()
1198 arm_smmu_rpm_put(smmu); in arm_smmu_attach_dev()
1206 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_map_pages()
1207 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_map_pages() local
1211 return -ENODEV; in arm_smmu_map_pages()
1213 arm_smmu_rpm_get(smmu); in arm_smmu_map_pages()
1214 ret = ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, gfp, mapped); in arm_smmu_map_pages()
1215 arm_smmu_rpm_put(smmu); in arm_smmu_map_pages()
1224 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_unmap_pages()
1225 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_unmap_pages() local
1231 arm_smmu_rpm_get(smmu); in arm_smmu_unmap_pages()
1232 ret = ops->unmap_pages(ops, iova, pgsize, pgcount, iotlb_gather); in arm_smmu_unmap_pages()
1233 arm_smmu_rpm_put(smmu); in arm_smmu_unmap_pages()
1241 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_flush_iotlb_all() local
1243 if (smmu_domain->flush_ops) { in arm_smmu_flush_iotlb_all()
1244 arm_smmu_rpm_get(smmu); in arm_smmu_flush_iotlb_all()
1245 smmu_domain->flush_ops->tlb_flush_all(smmu_domain); in arm_smmu_flush_iotlb_all()
1246 arm_smmu_rpm_put(smmu); in arm_smmu_flush_iotlb_all()
1254 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iotlb_sync() local
1256 if (!smmu) in arm_smmu_iotlb_sync()
1259 arm_smmu_rpm_get(smmu); in arm_smmu_iotlb_sync()
1260 if (smmu->version == ARM_SMMU_V2 || in arm_smmu_iotlb_sync()
1261 smmu_domain->stage == ARM_SMMU_DOMAIN_S1) in arm_smmu_iotlb_sync()
1264 arm_smmu_tlb_sync_global(smmu); in arm_smmu_iotlb_sync()
1265 arm_smmu_rpm_put(smmu); in arm_smmu_iotlb_sync()
1272 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iova_to_phys_hard() local
1273 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_iova_to_phys_hard()
1274 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; in arm_smmu_iova_to_phys_hard()
1275 struct device *dev = smmu->dev; in arm_smmu_iova_to_phys_hard()
1280 int ret, idx = cfg->cbndx; in arm_smmu_iova_to_phys_hard()
1283 ret = arm_smmu_rpm_get(smmu); in arm_smmu_iova_to_phys_hard()
1287 spin_lock_irqsave(&smmu_domain->cb_lock, flags); in arm_smmu_iova_to_phys_hard()
1289 if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) in arm_smmu_iova_to_phys_hard()
1290 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1292 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1294 reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR; in arm_smmu_iova_to_phys_hard()
1297 spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); in arm_smmu_iova_to_phys_hard()
1301 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1302 return ops->iova_to_phys(ops, iova); in arm_smmu_iova_to_phys_hard()
1305 phys = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_PAR); in arm_smmu_iova_to_phys_hard()
1306 spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); in arm_smmu_iova_to_phys_hard()
1315 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1324 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; in arm_smmu_iova_to_phys()
1326 if (domain->type == IOMMU_DOMAIN_IDENTITY) in arm_smmu_iova_to_phys()
1332 if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && in arm_smmu_iova_to_phys()
1333 smmu_domain->stage == ARM_SMMU_DOMAIN_S1) in arm_smmu_iova_to_phys()
1336 return ops->iova_to_phys(ops, iova); in arm_smmu_iova_to_phys()
1344 * Return true here as the SMMU can always send out coherent in arm_smmu_capable()
1366 struct arm_smmu_device *smmu = NULL; in arm_smmu_probe_device() local
1372 ret = arm_smmu_register_legacy_master(dev, &smmu); in arm_smmu_probe_device()
1375 * If dev->iommu_fwspec is initally NULL, arm_smmu_register_legacy_master() in arm_smmu_probe_device()
1382 } else if (fwspec && fwspec->ops == &arm_smmu_ops) { in arm_smmu_probe_device()
1383 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
1385 return ERR_PTR(-ENODEV); in arm_smmu_probe_device()
1388 ret = -EINVAL; in arm_smmu_probe_device()
1389 for (i = 0; i < fwspec->num_ids; i++) { in arm_smmu_probe_device()
1390 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); in arm_smmu_probe_device()
1391 u16 mask = FIELD_GET(ARM_SMMU_SMR_MASK, fwspec->ids[i]); in arm_smmu_probe_device()
1393 if (sid & ~smmu->streamid_mask) { in arm_smmu_probe_device()
1394 dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n", in arm_smmu_probe_device()
1395 sid, smmu->streamid_mask); in arm_smmu_probe_device()
1398 if (mask & ~smmu->smr_mask_mask) { in arm_smmu_probe_device()
1399 dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n", in arm_smmu_probe_device()
1400 mask, smmu->smr_mask_mask); in arm_smmu_probe_device()
1405 ret = -ENOMEM; in arm_smmu_probe_device()
1411 cfg->smmu = smmu; in arm_smmu_probe_device()
1413 while (i--) in arm_smmu_probe_device()
1414 cfg->smendx[i] = INVALID_SMENDX; in arm_smmu_probe_device()
1416 ret = arm_smmu_rpm_get(smmu); in arm_smmu_probe_device()
1421 arm_smmu_rpm_put(smmu); in arm_smmu_probe_device()
1426 device_link_add(dev, smmu->dev, in arm_smmu_probe_device()
1429 return &smmu->iommu; in arm_smmu_probe_device()
1442 struct arm_smmu_device *smmu; in arm_smmu_release_device() local
1445 if (!fwspec || fwspec->ops != &arm_smmu_ops) in arm_smmu_release_device()
1449 smmu = cfg->smmu; in arm_smmu_release_device()
1451 ret = arm_smmu_rpm_get(smmu); in arm_smmu_release_device()
1457 arm_smmu_rpm_put(smmu); in arm_smmu_release_device()
1468 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_device_group() local
1473 if (group && smmu->s2crs[idx].group && in arm_smmu_device_group()
1474 group != smmu->s2crs[idx].group) in arm_smmu_device_group()
1475 return ERR_PTR(-EINVAL); in arm_smmu_device_group()
1477 group = smmu->s2crs[idx].group; in arm_smmu_device_group()
1493 smmu->s2crs[idx].group = group; in arm_smmu_device_group()
1503 switch(domain->type) { in arm_smmu_domain_get_attr()
1507 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); in arm_smmu_domain_get_attr()
1510 return -ENODEV; in arm_smmu_domain_get_attr()
1516 *(int *)data = smmu_domain->non_strict; in arm_smmu_domain_get_attr()
1519 return -ENODEV; in arm_smmu_domain_get_attr()
1523 return -EINVAL; in arm_smmu_domain_get_attr()
1533 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_domain_set_attr()
1535 switch(domain->type) { in arm_smmu_domain_set_attr()
1539 if (smmu_domain->smmu) { in arm_smmu_domain_set_attr()
1540 ret = -EPERM; in arm_smmu_domain_set_attr()
1545 smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; in arm_smmu_domain_set_attr()
1547 smmu_domain->stage = ARM_SMMU_DOMAIN_S1; in arm_smmu_domain_set_attr()
1550 ret = -ENODEV; in arm_smmu_domain_set_attr()
1556 smmu_domain->non_strict = *(int *)data; in arm_smmu_domain_set_attr()
1559 ret = -ENODEV; in arm_smmu_domain_set_attr()
1563 ret = -EINVAL; in arm_smmu_domain_set_attr()
1566 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_domain_set_attr()
1574 if (args->args_count > 0) in arm_smmu_of_xlate()
1575 fwid |= FIELD_PREP(ARM_SMMU_SMR_ID, args->args[0]); in arm_smmu_of_xlate()
1577 if (args->args_count > 1) in arm_smmu_of_xlate()
1578 fwid |= FIELD_PREP(ARM_SMMU_SMR_MASK, args->args[1]); in arm_smmu_of_xlate()
1579 else if (!of_property_read_u32(args->np, "stream-match-mask", &mask)) in arm_smmu_of_xlate()
1596 list_add_tail(®ion->list, head); in arm_smmu_get_resv_regions()
1604 const struct arm_smmu_impl *impl = cfg->smmu->impl; in arm_smmu_def_domain_type()
1606 if (impl && impl->def_domain_type) in arm_smmu_def_domain_type()
1607 return impl->def_domain_type(dev); in arm_smmu_def_domain_type()
1631 .pgsize_bitmap = -1UL, /* Restricted during device attach */
1634 static void arm_smmu_device_reset(struct arm_smmu_device *smmu) in arm_smmu_device_reset() argument
1640 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_device_reset()
1641 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); in arm_smmu_device_reset()
1647 for (i = 0; i < smmu->num_mapping_groups; ++i) in arm_smmu_device_reset()
1648 arm_smmu_write_sme(smmu, i); in arm_smmu_device_reset()
1651 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_smmu_device_reset()
1652 arm_smmu_write_context_bank(smmu, i); in arm_smmu_device_reset()
1653 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); in arm_smmu_device_reset()
1657 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1658 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLNSNH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1660 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); in arm_smmu_device_reset()
1682 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_device_reset()
1685 if (smmu->features & ARM_SMMU_FEAT_EXIDS) in arm_smmu_device_reset()
1688 if (smmu->impl && smmu->impl->reset) in arm_smmu_device_reset()
1689 smmu->impl->reset(smmu); in arm_smmu_device_reset()
1692 arm_smmu_tlb_sync_global(smmu); in arm_smmu_device_reset()
1693 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); in arm_smmu_device_reset()
1715 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) in arm_smmu_device_cfg_probe() argument
1719 bool cttw_reg, cttw_fw = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_cfg_probe()
1722 dev_notice(smmu->dev, "probing hardware configuration...\n"); in arm_smmu_device_cfg_probe()
1723 dev_notice(smmu->dev, "SMMUv%d with:\n", in arm_smmu_device_cfg_probe()
1724 smmu->version == ARM_SMMU_V2 ? 2 : 1); in arm_smmu_device_cfg_probe()
1727 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID0); in arm_smmu_device_cfg_probe()
1736 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_cfg_probe()
1737 dev_notice(smmu->dev, "\tstage 1 translation\n"); in arm_smmu_device_cfg_probe()
1741 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_cfg_probe()
1742 dev_notice(smmu->dev, "\tstage 2 translation\n"); in arm_smmu_device_cfg_probe()
1746 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; in arm_smmu_device_cfg_probe()
1747 dev_notice(smmu->dev, "\tnested translation\n"); in arm_smmu_device_cfg_probe()
1750 if (!(smmu->features & in arm_smmu_device_cfg_probe()
1752 dev_err(smmu->dev, "\tno translation support!\n"); in arm_smmu_device_cfg_probe()
1753 return -ENODEV; in arm_smmu_device_cfg_probe()
1757 ((smmu->version < ARM_SMMU_V2) || !(id & ARM_SMMU_ID0_ATOSNS))) { in arm_smmu_device_cfg_probe()
1758 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; in arm_smmu_device_cfg_probe()
1759 dev_notice(smmu->dev, "\taddress translation ops\n"); in arm_smmu_device_cfg_probe()
1770 dev_notice(smmu->dev, "\t%scoherent table walk\n", in arm_smmu_device_cfg_probe()
1771 cttw_fw ? "" : "non-"); in arm_smmu_device_cfg_probe()
1773 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1777 if (smmu->version == ARM_SMMU_V2 && id & ARM_SMMU_ID0_EXIDS) { in arm_smmu_device_cfg_probe()
1778 smmu->features |= ARM_SMMU_FEAT_EXIDS; in arm_smmu_device_cfg_probe()
1783 smmu->streamid_mask = size - 1; in arm_smmu_device_cfg_probe()
1785 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; in arm_smmu_device_cfg_probe()
1788 dev_err(smmu->dev, in arm_smmu_device_cfg_probe()
1789 "stream-matching supported, but no SMRs present!\n"); in arm_smmu_device_cfg_probe()
1790 return -ENODEV; in arm_smmu_device_cfg_probe()
1793 /* Zero-initialised to mark as invalid */ in arm_smmu_device_cfg_probe()
1794 smmu->smrs = devm_kcalloc(smmu->dev, size, sizeof(*smmu->smrs), in arm_smmu_device_cfg_probe()
1796 if (!smmu->smrs) in arm_smmu_device_cfg_probe()
1797 return -ENOMEM; in arm_smmu_device_cfg_probe()
1799 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1802 /* s2cr->type == 0 means translation, so initialise explicitly */ in arm_smmu_device_cfg_probe()
1803 smmu->s2crs = devm_kmalloc_array(smmu->dev, size, sizeof(*smmu->s2crs), in arm_smmu_device_cfg_probe()
1805 if (!smmu->s2crs) in arm_smmu_device_cfg_probe()
1806 return -ENOMEM; in arm_smmu_device_cfg_probe()
1808 smmu->s2crs[i] = s2cr_init_val; in arm_smmu_device_cfg_probe()
1810 smmu->num_mapping_groups = size; in arm_smmu_device_cfg_probe()
1811 mutex_init(&smmu->stream_map_mutex); in arm_smmu_device_cfg_probe()
1812 spin_lock_init(&smmu->global_sync_lock); in arm_smmu_device_cfg_probe()
1814 if (smmu->version < ARM_SMMU_V2 || in arm_smmu_device_cfg_probe()
1816 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L; in arm_smmu_device_cfg_probe()
1818 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_S; in arm_smmu_device_cfg_probe()
1822 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID1); in arm_smmu_device_cfg_probe()
1823 smmu->pgshift = (id & ARM_SMMU_ID1_PAGESIZE) ? 16 : 12; in arm_smmu_device_cfg_probe()
1825 /* Check for size mismatch of SMMU address space from mapped region */ in arm_smmu_device_cfg_probe()
1827 if (smmu->numpage != 2 * size << smmu->pgshift) in arm_smmu_device_cfg_probe()
1828 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1829 "SMMU address space size (0x%x) differs from mapped region size (0x%x)!\n", in arm_smmu_device_cfg_probe()
1830 2 * size << smmu->pgshift, smmu->numpage); in arm_smmu_device_cfg_probe()
1832 smmu->numpage = size; in arm_smmu_device_cfg_probe()
1834 smmu->num_s2_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMS2CB, id); in arm_smmu_device_cfg_probe()
1835 smmu->num_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMCB, id); in arm_smmu_device_cfg_probe()
1836 if (smmu->num_s2_context_banks > smmu->num_context_banks) { in arm_smmu_device_cfg_probe()
1837 dev_err(smmu->dev, "impossible number of S2 context banks!\n"); in arm_smmu_device_cfg_probe()
1838 return -ENODEV; in arm_smmu_device_cfg_probe()
1840 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", in arm_smmu_device_cfg_probe()
1841 smmu->num_context_banks, smmu->num_s2_context_banks); in arm_smmu_device_cfg_probe()
1842 smmu->cbs = devm_kcalloc(smmu->dev, smmu->num_context_banks, in arm_smmu_device_cfg_probe()
1843 sizeof(*smmu->cbs), GFP_KERNEL); in arm_smmu_device_cfg_probe()
1844 if (!smmu->cbs) in arm_smmu_device_cfg_probe()
1845 return -ENOMEM; in arm_smmu_device_cfg_probe()
1848 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID2); in arm_smmu_device_cfg_probe()
1850 smmu->ipa_size = size; in arm_smmu_device_cfg_probe()
1854 smmu->pa_size = size; in arm_smmu_device_cfg_probe()
1857 smmu->features |= ARM_SMMU_FEAT_VMID16; in arm_smmu_device_cfg_probe()
1864 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size))) in arm_smmu_device_cfg_probe()
1865 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1868 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_device_cfg_probe()
1869 smmu->va_size = smmu->ipa_size; in arm_smmu_device_cfg_probe()
1870 if (smmu->version == ARM_SMMU_V1_64K) in arm_smmu_device_cfg_probe()
1871 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1874 smmu->va_size = arm_smmu_id_size_to_bits(size); in arm_smmu_device_cfg_probe()
1876 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_4K; in arm_smmu_device_cfg_probe()
1878 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_16K; in arm_smmu_device_cfg_probe()
1880 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1883 if (smmu->impl && smmu->impl->cfg_probe) { in arm_smmu_device_cfg_probe()
1884 ret = smmu->impl->cfg_probe(smmu); in arm_smmu_device_cfg_probe()
1890 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) in arm_smmu_device_cfg_probe()
1891 smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M; in arm_smmu_device_cfg_probe()
1892 if (smmu->features & in arm_smmu_device_cfg_probe()
1894 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_cfg_probe()
1895 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_16K) in arm_smmu_device_cfg_probe()
1896 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_cfg_probe()
1897 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K) in arm_smmu_device_cfg_probe()
1898 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_cfg_probe()
1900 if (arm_smmu_ops.pgsize_bitmap == -1UL) in arm_smmu_device_cfg_probe()
1901 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1903 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1904 dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", in arm_smmu_device_cfg_probe()
1905 smmu->pgsize_bitmap); in arm_smmu_device_cfg_probe()
1908 if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) in arm_smmu_device_cfg_probe()
1909 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", in arm_smmu_device_cfg_probe()
1910 smmu->va_size, smmu->ipa_size); in arm_smmu_device_cfg_probe()
1912 if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) in arm_smmu_device_cfg_probe()
1913 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", in arm_smmu_device_cfg_probe()
1914 smmu->ipa_size, smmu->pa_size); in arm_smmu_device_cfg_probe()
1935 { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
1936 { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
1937 { .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
1938 { .compatible = "arm,mmu-401", .data = &arm_mmu401 },
1939 { .compatible = "arm,mmu-500", .data = &arm_mmu500 },
1940 { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
1941 { .compatible = "nvidia,smmu-500", .data = &arm_mmu500 },
1942 { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
1948 static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu) in acpi_smmu_get_data() argument
1955 smmu->version = ARM_SMMU_V1; in acpi_smmu_get_data()
1956 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1959 smmu->version = ARM_SMMU_V1_64K; in acpi_smmu_get_data()
1960 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1963 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1964 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1967 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1968 smmu->model = ARM_MMU500; in acpi_smmu_get_data()
1971 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1972 smmu->model = CAVIUM_SMMUV2; in acpi_smmu_get_data()
1975 ret = -ENODEV; in acpi_smmu_get_data()
1982 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
1984 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
1991 iort_smmu = (struct acpi_iort_smmu *)node->node_data; in arm_smmu_device_acpi_probe()
1993 ret = acpi_smmu_get_data(iort_smmu->model, smmu); in arm_smmu_device_acpi_probe()
1998 smmu->num_global_irqs = 1; in arm_smmu_device_acpi_probe()
2000 if (iort_smmu->flags & ACPI_IORT_SMMU_COHERENT_WALK) in arm_smmu_device_acpi_probe()
2001 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_acpi_probe()
2007 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
2009 return -ENODEV; in arm_smmu_device_acpi_probe()
2014 struct arm_smmu_device *smmu) in arm_smmu_device_dt_probe() argument
2017 struct device *dev = &pdev->dev; in arm_smmu_device_dt_probe()
2020 if (of_property_read_u32(dev->of_node, "#global-interrupts", in arm_smmu_device_dt_probe()
2021 &smmu->num_global_irqs)) { in arm_smmu_device_dt_probe()
2022 dev_err(dev, "missing #global-interrupts property\n"); in arm_smmu_device_dt_probe()
2023 return -ENODEV; in arm_smmu_device_dt_probe()
2027 smmu->version = data->version; in arm_smmu_device_dt_probe()
2028 smmu->model = data->model; in arm_smmu_device_dt_probe()
2030 legacy_binding = of_find_property(dev->of_node, "mmu-masters", NULL); in arm_smmu_device_dt_probe()
2033 pr_notice("deprecated \"mmu-masters\" DT property in use; %s support unavailable\n", in arm_smmu_device_dt_probe()
2034 IS_ENABLED(CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS) ? "DMA API" : "SMMU"); in arm_smmu_device_dt_probe()
2041 return -ENODEV; in arm_smmu_device_dt_probe()
2044 if (of_dma_is_coherent(dev->of_node)) in arm_smmu_device_dt_probe()
2045 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_dt_probe()
2100 struct arm_smmu_device *smmu; in arm_smmu_device_probe() local
2101 struct device *dev = &pdev->dev; in arm_smmu_device_probe()
2105 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); in arm_smmu_device_probe()
2106 if (!smmu) { in arm_smmu_device_probe()
2108 return -ENOMEM; in arm_smmu_device_probe()
2110 smmu->dev = dev; in arm_smmu_device_probe()
2112 if (dev->of_node) in arm_smmu_device_probe()
2113 err = arm_smmu_device_dt_probe(pdev, smmu); in arm_smmu_device_probe()
2115 err = arm_smmu_device_acpi_probe(pdev, smmu); in arm_smmu_device_probe()
2120 smmu->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in arm_smmu_device_probe()
2121 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
2122 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
2123 ioaddr = res->start; in arm_smmu_device_probe()
2128 smmu->numpage = resource_size(res); in arm_smmu_device_probe()
2130 smmu = arm_smmu_impl_init(smmu); in arm_smmu_device_probe()
2131 if (IS_ERR(smmu)) in arm_smmu_device_probe()
2132 return PTR_ERR(smmu); in arm_smmu_device_probe()
2137 if (num_irqs > smmu->num_global_irqs) in arm_smmu_device_probe()
2138 smmu->num_context_irqs++; in arm_smmu_device_probe()
2141 if (!smmu->num_context_irqs) { in arm_smmu_device_probe()
2143 num_irqs, smmu->num_global_irqs + 1); in arm_smmu_device_probe()
2144 return -ENODEV; in arm_smmu_device_probe()
2147 smmu->irqs = devm_kcalloc(dev, num_irqs, sizeof(*smmu->irqs), in arm_smmu_device_probe()
2149 if (!smmu->irqs) { in arm_smmu_device_probe()
2151 return -ENOMEM; in arm_smmu_device_probe()
2158 return -ENODEV; in arm_smmu_device_probe()
2159 smmu->irqs[i] = irq; in arm_smmu_device_probe()
2162 err = devm_clk_bulk_get_all(dev, &smmu->clks); in arm_smmu_device_probe()
2167 smmu->num_clks = err; in arm_smmu_device_probe()
2169 err = clk_bulk_prepare_enable(smmu->num_clks, smmu->clks); in arm_smmu_device_probe()
2173 err = arm_smmu_device_cfg_probe(smmu); in arm_smmu_device_probe()
2177 if (smmu->version == ARM_SMMU_V2) { in arm_smmu_device_probe()
2178 if (smmu->num_context_banks > smmu->num_context_irqs) { in arm_smmu_device_probe()
2181 smmu->num_context_irqs, smmu->num_context_banks); in arm_smmu_device_probe()
2182 return -ENODEV; in arm_smmu_device_probe()
2186 smmu->num_context_irqs = smmu->num_context_banks; in arm_smmu_device_probe()
2189 if (smmu->impl && smmu->impl->global_fault) in arm_smmu_device_probe()
2190 global_fault = smmu->impl->global_fault; in arm_smmu_device_probe()
2194 for (i = 0; i < smmu->num_global_irqs; ++i) { in arm_smmu_device_probe()
2195 err = devm_request_irq(smmu->dev, smmu->irqs[i], in arm_smmu_device_probe()
2198 "arm-smmu global fault", in arm_smmu_device_probe()
2199 smmu); in arm_smmu_device_probe()
2202 i, smmu->irqs[i]); in arm_smmu_device_probe()
2207 err = iommu_device_sysfs_add(&smmu->iommu, smmu->dev, NULL, in arm_smmu_device_probe()
2208 "smmu.%pa", &ioaddr); in arm_smmu_device_probe()
2214 iommu_device_set_ops(&smmu->iommu, &arm_smmu_ops); in arm_smmu_device_probe()
2215 iommu_device_set_fwnode(&smmu->iommu, dev->fwnode); in arm_smmu_device_probe()
2217 err = iommu_device_register(&smmu->iommu); in arm_smmu_device_probe()
2223 platform_set_drvdata(pdev, smmu); in arm_smmu_device_probe()
2224 arm_smmu_device_reset(smmu); in arm_smmu_device_probe()
2225 arm_smmu_test_smr_masks(smmu); in arm_smmu_device_probe()
2228 * We want to avoid touching dev->power.lock in fastpaths unless in arm_smmu_device_probe()
2229 * it's really going to do something useful - pm_runtime_enabled() in arm_smmu_device_probe()
2233 if (dev->pm_domain) { in arm_smmu_device_probe()
2239 * For ACPI and generic DT bindings, an SMMU will be probed before in arm_smmu_device_probe()
2241 * ready to handle default domain setup as soon as any SMMU exists. in arm_smmu_device_probe()
2251 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_remove() local
2253 if (!smmu) in arm_smmu_device_remove()
2254 return -ENODEV; in arm_smmu_device_remove()
2256 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) in arm_smmu_device_remove()
2257 dev_notice(&pdev->dev, "disabling translation\n"); in arm_smmu_device_remove()
2260 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
2261 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
2263 arm_smmu_rpm_get(smmu); in arm_smmu_device_remove()
2265 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, ARM_SMMU_sCR0_CLIENTPD); in arm_smmu_device_remove()
2266 arm_smmu_rpm_put(smmu); in arm_smmu_device_remove()
2268 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_device_remove()
2269 pm_runtime_force_suspend(smmu->dev); in arm_smmu_device_remove()
2271 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_device_remove()
2273 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_device_remove()
2284 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_resume() local
2287 ret = clk_bulk_enable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_resume()
2291 arm_smmu_device_reset(smmu); in arm_smmu_runtime_resume()
2298 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_suspend() local
2300 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_suspend()
2329 .name = "arm-smmu",
2340 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2342 MODULE_ALIAS("platform:arm-smmu");