Lines Matching +full:sc7180 +full:- +full:mss
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/adreno-smmu-priv.h>
11 #include "arm-smmu.h"
25 for (i = 0; i < smmu->num_mapping_groups; i++) { in qcom_sdm845_smmu500_cfg_probe()
29 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in qcom_sdm845_smmu500_cfg_probe()
30 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); in qcom_sdm845_smmu500_cfg_probe()
31 if (smmu->features & ARM_SMMU_FEAT_EXIDS) in qcom_sdm845_smmu500_cfg_probe()
32 smmu->smrs[i].valid = FIELD_GET( in qcom_sdm845_smmu500_cfg_probe()
36 smmu->smrs[i].valid = FIELD_GET( in qcom_sdm845_smmu500_cfg_probe()
40 smmu->s2crs[i].group = NULL; in qcom_sdm845_smmu500_cfg_probe()
41 smmu->s2crs[i].count = 0; in qcom_sdm845_smmu500_cfg_probe()
42 smmu->s2crs[i].type = FIELD_GET(ARM_SMMU_S2CR_TYPE, s2cr); in qcom_sdm845_smmu500_cfg_probe()
43 smmu->s2crs[i].privcfg = FIELD_GET(ARM_SMMU_S2CR_PRIVCFG, s2cr); in qcom_sdm845_smmu500_cfg_probe()
44 smmu->s2crs[i].cbndx = FIELD_GET(ARM_SMMU_S2CR_CBNDX, s2cr); in qcom_sdm845_smmu500_cfg_probe()
46 if (!smmu->smrs[i].valid) in qcom_sdm845_smmu500_cfg_probe()
49 smmu->s2crs[i].pinned = true; in qcom_sdm845_smmu500_cfg_probe()
50 bitmap_set(smmu->context_map, smmu->s2crs[i].cbndx, 1); in qcom_sdm845_smmu500_cfg_probe()
65 * identify it and configure it for per-instance pagetables in qcom_adreno_smmu_is_gpu_device()
67 for (i = 0; i < fwspec->num_ids; i++) { in qcom_adreno_smmu_is_gpu_device()
68 u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); in qcom_adreno_smmu_is_gpu_device()
82 io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); in qcom_adreno_smmu_get_ttbr1_cfg()
83 return &pgtable->cfg; in qcom_adreno_smmu_get_ttbr1_cfg()
88 * The GPU driver will call this to enable TTBR0 when per-instance pagetables
96 struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); in qcom_adreno_smmu_set_ttbr0_cfg()
97 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_set_ttbr0_cfg()
98 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; in qcom_adreno_smmu_set_ttbr0_cfg()
101 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) in qcom_adreno_smmu_set_ttbr0_cfg()
102 return -EINVAL; in qcom_adreno_smmu_set_ttbr0_cfg()
107 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) in qcom_adreno_smmu_set_ttbr0_cfg()
108 return -EINVAL; in qcom_adreno_smmu_set_ttbr0_cfg()
111 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); in qcom_adreno_smmu_set_ttbr0_cfg()
112 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
114 u32 tcr = cb->tcr[0]; in qcom_adreno_smmu_set_ttbr0_cfg()
117 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) in qcom_adreno_smmu_set_ttbr0_cfg()
118 return -EINVAL; in qcom_adreno_smmu_set_ttbr0_cfg()
123 cb->tcr[0] = tcr; in qcom_adreno_smmu_set_ttbr0_cfg()
124 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in qcom_adreno_smmu_set_ttbr0_cfg()
125 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
128 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); in qcom_adreno_smmu_set_ttbr0_cfg()
148 count = smmu->num_context_banks; in qcom_adreno_smmu_alloc_context_bank()
151 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); in qcom_adreno_smmu_alloc_context_bank()
164 * All targets that use the qcom,adreno-smmu compatible string *should* in qcom_adreno_smmu_init_context()
165 * be AARCH64 stage 1 but double check because the arm-smmu code assumes in qcom_adreno_smmu_init_context()
168 if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && in qcom_adreno_smmu_init_context()
169 (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) in qcom_adreno_smmu_init_context()
170 pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; in qcom_adreno_smmu_init_context()
177 priv->cookie = smmu_domain; in qcom_adreno_smmu_init_context()
178 priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; in qcom_adreno_smmu_init_context()
179 priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; in qcom_adreno_smmu_init_context()
193 { .compatible = "qcom,sc7180-mdss" },
194 { .compatible = "qcom,sc7180-mss-pil" },
195 { .compatible = "qcom,sdm845-mdss" },
196 { .compatible = "qcom,sdm845-mss-pil" },
202 unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); in qcom_smmu_cfg_probe()
220 qsmmu->bypass_quirk = true; in qcom_smmu_cfg_probe()
221 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; in qcom_smmu_cfg_probe()
223 set_bit(qsmmu->bypass_cbndx, smmu->context_map); in qcom_smmu_cfg_probe()
225 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); in qcom_smmu_cfg_probe()
228 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); in qcom_smmu_cfg_probe()
231 for (i = 0; i < smmu->num_mapping_groups; i++) { in qcom_smmu_cfg_probe()
237 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); in qcom_smmu_cfg_probe()
238 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in qcom_smmu_cfg_probe()
239 smmu->smrs[i].valid = true; in qcom_smmu_cfg_probe()
241 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; in qcom_smmu_cfg_probe()
242 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; in qcom_smmu_cfg_probe()
243 smmu->s2crs[i].cbndx = 0xff; in qcom_smmu_cfg_probe()
252 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; in qcom_smmu_write_s2cr()
254 u32 cbndx = s2cr->cbndx; in qcom_smmu_write_s2cr()
255 u32 type = s2cr->type; in qcom_smmu_write_s2cr()
258 if (qsmmu->bypass_quirk) { in qcom_smmu_write_s2cr()
267 cbndx = qsmmu->bypass_cbndx; in qcom_smmu_write_s2cr()
281 FIELD_PREP(ARM_SMMU_S2CR_PRIVCFG, s2cr->privcfg); in qcom_smmu_write_s2cr()
298 * To address performance degradation in non-real time clients, in qcom_sdm845_smmu500_reset()
299 * such as USB and UFS, turn off wait-for-safe on sdm845 based boards, in qcom_sdm845_smmu500_reset()
301 * call handlers to turn on/off the wait-for-safe logic. in qcom_sdm845_smmu500_reset()
305 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); in qcom_sdm845_smmu500_reset()
312 const struct device_node *np = smmu->dev->of_node; in qcom_smmu500_reset()
316 if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) in qcom_smmu500_reset()
344 return ERR_PTR(-EPROBE_DEFER); in qcom_smmu_create()
346 qsmmu = devm_kzalloc(smmu->dev, sizeof(*qsmmu), GFP_KERNEL); in qcom_smmu_create()
348 return ERR_PTR(-ENOMEM); in qcom_smmu_create()
350 qsmmu->smmu = *smmu; in qcom_smmu_create()
352 qsmmu->smmu.impl = impl; in qcom_smmu_create()
353 devm_kfree(smmu->dev, smmu); in qcom_smmu_create()
355 return &qsmmu->smmu; in qcom_smmu_create()