arm/arm-smmu/arm-smmu-qcom.c

6 #include <linux/adreno-smmu-priv.h>
11 #include "arm-smmu.h"
14 	struct arm_smmu_device smmu;  member
19 static int qcom_sdm845_smmu500_cfg_probe(struct arm_smmu_device *smmu)  in qcom_sdm845_smmu500_cfg_probe()  argument
25 	for (i = 0; i < smmu->num_mapping_groups; i++) {  in qcom_sdm845_smmu500_cfg_probe()
26 		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));  in qcom_sdm845_smmu500_cfg_probe()
27 		s2cr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_S2CR(i));  in qcom_sdm845_smmu500_cfg_probe()
29 		smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);  in qcom_sdm845_smmu500_cfg_probe()
30 		smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);  in qcom_sdm845_smmu500_cfg_probe()
31 		if (smmu->features & ARM_SMMU_FEAT_EXIDS)  in qcom_sdm845_smmu500_cfg_probe()
32 			smmu->smrs[i].valid = FIELD_GET(  in qcom_sdm845_smmu500_cfg_probe()
36 			smmu->smrs[i].valid = FIELD_GET(  in qcom_sdm845_smmu500_cfg_probe()
40 		smmu->s2crs[i].group = NULL;  in qcom_sdm845_smmu500_cfg_probe()
41 		smmu->s2crs[i].count = 0;  in qcom_sdm845_smmu500_cfg_probe()
42 		smmu->s2crs[i].type = FIELD_GET(ARM_SMMU_S2CR_TYPE, s2cr);  in qcom_sdm845_smmu500_cfg_probe()
43 		smmu->s2crs[i].privcfg = FIELD_GET(ARM_SMMU_S2CR_PRIVCFG, s2cr);  in qcom_sdm845_smmu500_cfg_probe()
44 		smmu->s2crs[i].cbndx = FIELD_GET(ARM_SMMU_S2CR_CBNDX, s2cr);  in qcom_sdm845_smmu500_cfg_probe()
46 		if (!smmu->smrs[i].valid)  in qcom_sdm845_smmu500_cfg_probe()
49 		smmu->s2crs[i].pinned = true;  in qcom_sdm845_smmu500_cfg_probe()
50 		bitmap_set(smmu->context_map, smmu->s2crs[i].cbndx, 1);  in qcom_sdm845_smmu500_cfg_probe()
98 	struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx];  in qcom_adreno_smmu_set_ttbr0_cfg()
128 	arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx);  in qcom_adreno_smmu_set_ttbr0_cfg()
134 					       struct arm_smmu_device *smmu,  in qcom_adreno_smmu_alloc_context_bank()  argument
148 		count = smmu->num_context_banks;  in qcom_adreno_smmu_alloc_context_bank()
151 	return __arm_smmu_alloc_bitmap(smmu->context_map, start, count);  in qcom_adreno_smmu_alloc_context_bank()
164 	 * All targets that use the qcom,adreno-smmu compatible string *should*  in qcom_adreno_smmu_init_context()
165 	 * be AARCH64 stage 1 but double check because the arm-smmu code assumes  in qcom_adreno_smmu_init_context()
184 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)  in to_qcom_smmu()  argument
186 	return container_of(smmu, struct qcom_smmu, smmu);  in to_qcom_smmu()
200 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)  in qcom_smmu_cfg_probe()  argument
202 	unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1);  in qcom_smmu_cfg_probe()
203 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_cfg_probe()
217 	arm_smmu_gr0_write(smmu, last_s2cr, reg);  in qcom_smmu_cfg_probe()
218 	reg = arm_smmu_gr0_read(smmu, last_s2cr);  in qcom_smmu_cfg_probe()
221 		qsmmu->bypass_cbndx = smmu->num_context_banks - 1;  in qcom_smmu_cfg_probe()
223 		set_bit(qsmmu->bypass_cbndx, smmu->context_map);  in qcom_smmu_cfg_probe()
225 		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);  in qcom_smmu_cfg_probe()
228 		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);  in qcom_smmu_cfg_probe()
231 	for (i = 0; i < smmu->num_mapping_groups; i++) {  in qcom_smmu_cfg_probe()
232 		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));  in qcom_smmu_cfg_probe()
237 			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);  in qcom_smmu_cfg_probe()
238 			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);  in qcom_smmu_cfg_probe()
239 			smmu->smrs[i].valid = true;  in qcom_smmu_cfg_probe()
241 			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;  in qcom_smmu_cfg_probe()
242 			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;  in qcom_smmu_cfg_probe()
243 			smmu->s2crs[i].cbndx = 0xff;  in qcom_smmu_cfg_probe()
250 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)  in qcom_smmu_write_s2cr()  argument
252 	struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx;  in qcom_smmu_write_s2cr()
253 	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);  in qcom_smmu_write_s2cr()
282 	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);  in qcom_smmu_write_s2cr()
293 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)  in qcom_sdm845_smmu500_reset()  argument
305 		dev_warn(smmu->dev, "Failed to turn off SAFE logic\n");  in qcom_sdm845_smmu500_reset()
310 static int qcom_smmu500_reset(struct arm_smmu_device *smmu)  in qcom_smmu500_reset()  argument
312 	const struct device_node *np = smmu->dev->of_node;  in qcom_smmu500_reset()
314 	arm_mmu500_reset(smmu);  in qcom_smmu500_reset()
316 	if (of_device_is_compatible(np, "qcom,sdm845-smmu-500"))  in qcom_smmu500_reset()
317 		return qcom_sdm845_smmu500_reset(smmu);  in qcom_smmu500_reset()
337 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,  in qcom_smmu_create()  argument
346 	qsmmu = devm_kzalloc(smmu->dev, sizeof(*qsmmu), GFP_KERNEL);  in qcom_smmu_create()
350 	qsmmu->smmu = *smmu;  in qcom_smmu_create()
352 	qsmmu->smmu.impl = impl;  in qcom_smmu_create()
353 	devm_kfree(smmu->dev, smmu);  in qcom_smmu_create()
355 	return &qsmmu->smmu;  in qcom_smmu_create()
358 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)  in qcom_smmu_impl_init()  argument
360 	return qcom_smmu_create(smmu, &qcom_smmu_impl);  in qcom_smmu_impl_init()
363 struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu)  in qcom_adreno_smmu_impl_init()  argument
365 	return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);  in qcom_adreno_smmu_impl_init()