Lines Matching full:51
128 #define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6)
158 #define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
178 #define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5)
200 #define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6)
213 #define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
252 #define STRTAB_STE_2_S2AA64 (1UL << 51)
257 #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)
271 #define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12)
295 #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4)
344 #define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12)
364 #define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2)
379 #define PRIQ_0_SSID GENMASK_ULL(51, 32)