580 	u32 pasid;  in iommu_print_event()  local
585 	pasid   = (event[0] & EVENT_DOMID_MASK_HI) |  in iommu_print_event()
601 		amd_iommu_report_page_fault(devid, pasid, address, flags);  in iommu_print_event()
609 			pasid, address, flags);  in iommu_print_event()
621 			pasid, address, flags);  in iommu_print_event()
639 			pasid, address, flags);  in iommu_print_event()
648 		pasid = PPR_PASID(*((u64 *)__evt));  in iommu_print_event()
652 			pasid, address, flags, tag);  in iommu_print_event()
687 	fault.pasid     = PPR_PASID(raw[0]);  in iommu_handle_ppr_entry()
1000 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,  in build_inv_iommu_pasid()  argument
1007 	cmd->data[0]  = pasid;  in build_inv_iommu_pasid()
1018 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,  in build_inv_iotlb_pasid()  argument
1026 	cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;  in build_inv_iotlb_pasid()
1029 	cmd->data[1] |= (pasid & 0xff) << 16;  in build_inv_iotlb_pasid()
1038 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,  in build_complete_ppr()  argument
1045 		cmd->data[1]  = pasid;  in build_complete_ppr()
2879 static int __flush_pasid(struct protection_domain *domain, u32 pasid,  in __flush_pasid()  argument
2889 	build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);  in __flush_pasid()
2922 		build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,  in __flush_pasid()
2940 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,  in __amd_iommu_flush_page()  argument
2943 	return __flush_pasid(domain, pasid, address, false);  in __amd_iommu_flush_page()
2946 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,  in amd_iommu_flush_page()  argument
2954 	ret = __amd_iommu_flush_page(domain, pasid, address);  in amd_iommu_flush_page()
2961 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)  in __amd_iommu_flush_tlb()  argument
2963 	return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,  in __amd_iommu_flush_tlb()
2967 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)  in amd_iommu_flush_tlb()  argument
2974 	ret = __amd_iommu_flush_tlb(domain, pasid);  in amd_iommu_flush_tlb()
2981 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)  in __get_gcr3_pte()  argument
2988 		index = (pasid >> (9 * level)) & 0x1ff;  in __get_gcr3_pte()
3013 static int __set_gcr3(struct protection_domain *domain, u32 pasid,  in __set_gcr3()  argument
3023 	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);  in __set_gcr3()
3029 	return __amd_iommu_flush_tlb(domain, pasid);  in __set_gcr3()
3032 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)  in __clear_gcr3()  argument
3041 	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);  in __clear_gcr3()
3047 	return __amd_iommu_flush_tlb(domain, pasid);  in __clear_gcr3()
3050 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,  in amd_iommu_domain_set_gcr3()  argument
3058 	ret = __set_gcr3(domain, pasid, cr3);  in amd_iommu_domain_set_gcr3()
3065 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)  in amd_iommu_domain_clear_gcr3()  argument
3072 	ret = __clear_gcr3(domain, pasid);  in amd_iommu_domain_clear_gcr3()
3079 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,  in amd_iommu_complete_ppr()  argument
3089 	build_complete_ppr(&cmd, dev_data->devid, pasid, status,  in amd_iommu_complete_ppr()