Lines Matching full:iommu
19 #include <linux/amd-iommu.h>
25 #include <asm/iommu.h>
98 * structure describing one IOMMU in the ACPI table. Typically followed by one
118 * A device entry describing which devices a specific IOMMU translates and
134 * An AMD IOMMU memory definition structure. It defines things like exclusion
199 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
205 * The rlookup table is used to find the IOMMU which is responsible
218 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
263 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
265 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
269 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
271 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
274 static void init_translation_status(struct amd_iommu *iommu) in init_translation_status() argument
278 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
280 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
306 struct amd_iommu *iommu; in check_feature_on_all_iommus() local
308 for_each_iommu(iommu) { in check_feature_on_all_iommus()
309 ret = iommu_feature(iommu, mask); in check_feature_on_all_iommus()
323 static void __init early_iommu_features_init(struct amd_iommu *iommu, in early_iommu_features_init() argument
327 iommu->features = h->efr_reg; in early_iommu_features_init()
332 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
336 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
337 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
341 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
343 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
344 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
345 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
348 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
352 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
353 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
357 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
359 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
360 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
365 * AMD IOMMU MMIO register space handling functions
367 * These functions are used to program the IOMMU device registers in
373 * This function set the exclusion range in the IOMMU. DMA accesses to the
376 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
378 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
379 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; in iommu_set_exclusion_range()
382 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
386 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
390 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
394 static void iommu_set_cwwb_range(struct amd_iommu *iommu) in iommu_set_cwwb_range() argument
396 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()
399 if (!iommu_feature(iommu, FEATURE_SNP)) in iommu_set_cwwb_range()
406 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
413 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
417 /* Programs the physical address of the device table into the IOMMU hardware */
418 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
422 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
426 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
430 /* Generic functions to enable/disable certain features of the IOMMU. */
431 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
435 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
437 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
440 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
444 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
446 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
449 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
453 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
456 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
460 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
462 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
465 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
467 if (!iommu->mmio_base) in iommu_disable()
471 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
474 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
475 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
477 /* Disable IOMMU GA_LOG */ in iommu_disable()
478 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in iommu_disable()
479 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in iommu_disable()
481 /* Disable IOMMU hardware itself */ in iommu_disable()
482 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
486 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
501 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
503 if (iommu->mmio_base) in iommu_unmap_mmio_space()
504 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
505 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
526 * The functions below belong to the first pass of AMD IOMMU ACPI table
550 * After reading the highest device id from the IOMMU PCI capability header
640 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
647 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
648 * write commands to that buffer later and the IOMMU will execute them
651 static int __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
653 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_command_buffer()
656 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
660 * This function restarts event logging in case the IOMMU experienced
663 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) in amd_iommu_restart_event_logging() argument
665 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in amd_iommu_restart_event_logging()
666 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in amd_iommu_restart_event_logging()
670 * This function resets the command buffer if the IOMMU stopped fetching
673 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
675 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
677 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
678 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
679 iommu->cmd_buf_head = 0; in amd_iommu_reset_cmd_buffer()
680 iommu->cmd_buf_tail = 0; in amd_iommu_reset_cmd_buffer()
682 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
689 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
693 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
695 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
698 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
701 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
707 static void iommu_disable_command_buffer(struct amd_iommu *iommu) in iommu_disable_command_buffer() argument
709 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable_command_buffer()
712 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
714 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
717 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, in iommu_alloc_4k_pages() argument
724 iommu_feature(iommu, FEATURE_SNP) && in iommu_alloc_4k_pages()
733 /* allocates the memory where the IOMMU will log its events to */
734 static int __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
736 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_event_buffer()
739 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
742 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
746 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
748 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
750 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
754 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
755 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
757 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
763 static void iommu_disable_event_buffer(struct amd_iommu *iommu) in iommu_disable_event_buffer() argument
765 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable_event_buffer()
768 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
770 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
773 /* allocates the memory where the IOMMU will log its events to */
774 static int __init alloc_ppr_log(struct amd_iommu *iommu) in alloc_ppr_log() argument
776 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_ppr_log()
779 return iommu->ppr_log ? 0 : -ENOMEM; in alloc_ppr_log()
782 static void iommu_enable_ppr_log(struct amd_iommu *iommu) in iommu_enable_ppr_log() argument
786 if (iommu->ppr_log == NULL) in iommu_enable_ppr_log()
789 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in iommu_enable_ppr_log()
791 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, in iommu_enable_ppr_log()
795 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_enable_ppr_log()
796 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_enable_ppr_log()
798 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); in iommu_enable_ppr_log()
799 iommu_feature_enable(iommu, CONTROL_PPR_EN); in iommu_enable_ppr_log()
802 static void __init free_ppr_log(struct amd_iommu *iommu) in free_ppr_log() argument
804 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); in free_ppr_log()
807 static void free_ga_log(struct amd_iommu *iommu) in free_ga_log() argument
810 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); in free_ga_log()
811 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); in free_ga_log()
815 static int iommu_ga_log_enable(struct amd_iommu *iommu) in iommu_ga_log_enable() argument
821 if (!iommu->ga_log) in iommu_ga_log_enable()
825 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
829 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_ga_log_enable()
830 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, in iommu_ga_log_enable()
832 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_ga_log_enable()
834 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, in iommu_ga_log_enable()
836 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_ga_log_enable()
837 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_ga_log_enable()
840 iommu_feature_enable(iommu, CONTROL_GAINT_EN); in iommu_ga_log_enable()
841 iommu_feature_enable(iommu, CONTROL_GALOG_EN); in iommu_ga_log_enable()
844 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
856 static int iommu_init_ga_log(struct amd_iommu *iommu) in iommu_init_ga_log() argument
862 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
864 if (!iommu->ga_log) in iommu_init_ga_log()
867 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
869 if (!iommu->ga_log_tail) in iommu_init_ga_log()
874 free_ga_log(iommu); in iommu_init_ga_log()
881 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) in alloc_cwwb_sem() argument
883 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); in alloc_cwwb_sem()
885 return iommu->cmd_sem ? 0 : -ENOMEM; in alloc_cwwb_sem()
888 static void __init free_cwwb_sem(struct amd_iommu *iommu) in free_cwwb_sem() argument
890 if (iommu->cmd_sem) in free_cwwb_sem()
891 free_page((unsigned long)iommu->cmd_sem); in free_cwwb_sem()
894 static void iommu_enable_xt(struct amd_iommu *iommu) in iommu_enable_xt() argument
903 iommu_feature_enable(iommu, CONTROL_XT_EN); in iommu_enable_xt()
907 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
909 if (!iommu_feature(iommu, FEATURE_GT)) in iommu_enable_gt()
912 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
939 struct amd_iommu *iommu; in copy_device_table() local
948 for_each_iommu(iommu) { in copy_device_table()
950 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); in copy_device_table()
951 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); in copy_device_table()
954 pr_err("IOMMU:%d should use the same dev table as others!\n", in copy_device_table()
955 iommu->index); in copy_device_table()
962 pr_err("The device table size of IOMMU:%d is not expected!\n", in copy_device_table()
963 iommu->index); in copy_device_table()
1044 /* Writes the specific IOMMU for a device into the rlookup table */
1045 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) in set_iommu_for_device() argument
1047 amd_iommu_rlookup_table[devid] = iommu; in set_iommu_for_device()
1054 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
1074 set_iommu_for_device(iommu, devid); in set_dev_entry_from_acpi()
1185 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1188 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
1210 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
1234 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); in init_iommu_from_acpi()
1246 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1276 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
1277 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
1309 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
1337 set_dev_entry_from_acpi(iommu, in init_iommu_from_acpi()
1340 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
1376 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1441 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1455 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
1457 free_cwwb_sem(iommu); in free_iommu_one()
1458 free_command_buffer(iommu); in free_iommu_one()
1459 free_event_buffer(iommu); in free_iommu_one()
1460 free_ppr_log(iommu); in free_iommu_one()
1461 free_ga_log(iommu); in free_iommu_one()
1462 iommu_unmap_mmio_space(iommu); in free_iommu_one()
1467 struct amd_iommu *iommu, *next; in free_iommu_all() local
1469 for_each_iommu_safe(iommu, next) { in free_iommu_all()
1470 list_del(&iommu->list); in free_iommu_all()
1471 free_iommu_one(iommu); in free_iommu_all()
1472 kfree(iommu); in free_iommu_all()
1477 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1482 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1491 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1492 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1498 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1500 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1501 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); in amd_iommu_erratum_746_workaround()
1504 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1508 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1513 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) in amd_iommu_ats_write_check_workaround() argument
1523 value = iommu_read_l2(iommu, 0x47); in amd_iommu_ats_write_check_workaround()
1529 iommu_write_l2(iommu, 0x47, value | BIT(0)); in amd_iommu_ats_write_check_workaround()
1531 pci_info(iommu->dev, "Applying ATS write check workaround\n"); in amd_iommu_ats_write_check_workaround()
1535 * This function clues the initialization function for one IOMMU
1537 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1539 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) in init_iommu_one() argument
1543 raw_spin_lock_init(&iommu->lock); in init_iommu_one()
1544 iommu->cmd_sem_val = 0; in init_iommu_one()
1546 /* Add IOMMU to internal data structures */ in init_iommu_one()
1547 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1548 iommu->index = amd_iommus_present++; in init_iommu_one()
1550 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1555 /* Index is fine - add IOMMU to the array */ in init_iommu_one()
1556 amd_iommus[iommu->index] = iommu; in init_iommu_one()
1559 * Copy data from ACPI table entry to the iommu struct in init_iommu_one()
1561 iommu->devid = h->devid; in init_iommu_one()
1562 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1563 iommu->pci_seg = h->pci_seg; in init_iommu_one()
1564 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1572 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1574 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1588 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1590 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1605 * the IOMMU MMIO access to MSI capability block registers in init_iommu_one()
1613 early_iommu_features_init(iommu, h); in init_iommu_one()
1620 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1621 iommu->mmio_phys_end); in init_iommu_one()
1622 if (!iommu->mmio_base) in init_iommu_one()
1625 if (alloc_cwwb_sem(iommu)) in init_iommu_one()
1628 if (alloc_command_buffer(iommu)) in init_iommu_one()
1631 if (alloc_event_buffer(iommu)) in init_iommu_one()
1634 iommu->int_enabled = false; in init_iommu_one()
1636 init_translation_status(iommu); in init_iommu_one()
1637 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_iommu_one()
1638 iommu_disable(iommu); in init_iommu_one()
1639 clear_translation_pre_enabled(iommu); in init_iommu_one()
1640 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", in init_iommu_one()
1641 iommu->index); in init_iommu_one()
1644 amd_iommu_pre_enabled = translation_pre_enabled(iommu); in init_iommu_one()
1646 ret = init_iommu_from_acpi(iommu, h); in init_iommu_one()
1650 ret = amd_iommu_create_irq_domain(iommu); in init_iommu_one()
1655 * Make sure IOMMU is not considered to translate itself. The IVRS in init_iommu_one()
1658 amd_iommu_rlookup_table[iommu->devid] = NULL; in init_iommu_one()
1690 * Iterates over all IOMMU entries in the ACPI table, allocates the
1691 * IOMMU structure and initializes it with init_iommu_one()
1697 struct amd_iommu *iommu; in init_iommu_all() local
1715 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1716 if (iommu == NULL) in init_iommu_all()
1719 ret = init_iommu_one(iommu, h); in init_iommu_all()
1731 static void init_iommu_perf_ctr(struct amd_iommu *iommu) in init_iommu_perf_ctr() argument
1734 struct pci_dev *pdev = iommu->dev; in init_iommu_perf_ctr()
1736 if (!iommu_feature(iommu, FEATURE_PC)) in init_iommu_perf_ctr()
1741 pci_info(pdev, "IOMMU performance counters supported\n"); in init_iommu_perf_ctr()
1743 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
1744 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
1745 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
1754 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_cap() local
1755 return sprintf(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
1763 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_features() local
1764 return sprintf(buf, "%llx\n", iommu->features); in amd_iommu_show_features()
1775 .name = "amd-iommu",
1786 * of the IOMMU Extended Feature Register [MMIO Offset 0030h].
1789 static void __init late_iommu_features_init(struct amd_iommu *iommu) in late_iommu_features_init() argument
1793 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) in late_iommu_features_init()
1797 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); in late_iommu_features_init()
1799 if (!iommu->features) { in late_iommu_features_init()
1800 iommu->features = features; in late_iommu_features_init()
1808 if (features != iommu->features) in late_iommu_features_init()
1810 features, iommu->features); in late_iommu_features_init()
1813 static int __init iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
1815 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
1818 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
1819 iommu->devid & 0xff); in iommu_init_pci()
1820 if (!iommu->dev) in iommu_init_pci()
1823 /* Prevent binding other PCI device drivers to IOMMU devices */ in iommu_init_pci()
1824 iommu->dev->match_driver = false; in iommu_init_pci()
1826 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
1827 &iommu->cap); in iommu_init_pci()
1829 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
1832 late_iommu_features_init(iommu); in iommu_init_pci()
1834 if (iommu_feature(iommu, FEATURE_GT)) { in iommu_init_pci()
1839 pasmax = iommu->features & FEATURE_PASID_MASK; in iommu_init_pci()
1847 glxval = iommu->features & FEATURE_GLXVAL_MASK; in iommu_init_pci()
1856 if (iommu_feature(iommu, FEATURE_GT) && in iommu_init_pci()
1857 iommu_feature(iommu, FEATURE_PPR)) { in iommu_init_pci()
1858 iommu->is_iommu_v2 = true; in iommu_init_pci()
1862 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) in iommu_init_pci()
1865 ret = iommu_init_ga_log(iommu); in iommu_init_pci()
1869 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) in iommu_init_pci()
1872 init_iommu_perf_ctr(iommu); in iommu_init_pci()
1874 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
1877 iommu->root_pdev = in iommu_init_pci()
1878 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, in iommu_init_pci()
1886 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
1887 &iommu->stored_addr_lo); in iommu_init_pci()
1888 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
1889 &iommu->stored_addr_hi); in iommu_init_pci()
1892 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
1896 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
1899 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
1902 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
1903 amd_iommu_ats_write_check_workaround(iommu); in iommu_init_pci()
1905 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, in iommu_init_pci()
1906 amd_iommu_groups, "ivhd%d", iommu->index); in iommu_init_pci()
1907 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops); in iommu_init_pci()
1908 iommu_device_register(&iommu->iommu); in iommu_init_pci()
1910 return pci_enable_device(iommu->dev); in iommu_init_pci()
1919 struct amd_iommu *iommu; in print_iommu_info() local
1921 for_each_iommu(iommu) { in print_iommu_info()
1922 struct pci_dev *pdev = iommu->dev; in print_iommu_info()
1925 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr); in print_iommu_info()
1927 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { in print_iommu_info()
1928 pr_info("Extended features (%#llx):", iommu->features); in print_iommu_info()
1931 if (iommu_feature(iommu, (1ULL << i))) in print_iommu_info()
1935 if (iommu->features & FEATURE_GAM_VAPIC) in print_iommu_info()
1952 struct amd_iommu *iommu; in amd_iommu_init_pci() local
1955 for_each_iommu(iommu) { in amd_iommu_init_pci()
1956 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
1961 iommu_set_cwwb_range(iommu); in amd_iommu_init_pci()
1978 for_each_iommu(iommu) in amd_iommu_init_pci()
1979 iommu_flush_all_caches(iommu); in amd_iommu_init_pci()
1996 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
2000 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
2004 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
2008 iommu); in iommu_setup_msi()
2011 pci_disable_msi(iommu->dev); in iommu_setup_msi()
2015 iommu->int_enabled = true; in iommu_setup_msi()
2030 static void iommu_update_intcapxt(struct amd_iommu *iommu) in iommu_update_intcapxt() argument
2033 u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET); in iommu_update_intcapxt()
2034 u32 addr_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET); in iommu_update_intcapxt()
2035 u32 data = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET); in iommu_update_intcapxt()
2048 * Current IOMMU implemtation uses the same IRQ for all in iommu_update_intcapxt()
2049 * 3 IOMMU interrupts. in iommu_update_intcapxt()
2051 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); in iommu_update_intcapxt()
2052 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); in iommu_update_intcapxt()
2053 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); in iommu_update_intcapxt()
2059 struct amd_iommu *iommu; in _irq_notifier_notify() local
2061 for_each_iommu(iommu) { in _irq_notifier_notify()
2062 if (iommu->dev->irq == notify->irq) { in _irq_notifier_notify()
2063 iommu_update_intcapxt(iommu); in _irq_notifier_notify()
2073 static int iommu_init_intcapxt(struct amd_iommu *iommu) in iommu_init_intcapxt() argument
2076 struct irq_affinity_notify *notify = &iommu->intcapxt_notify; in iommu_init_intcapxt()
2089 notify->irq = iommu->dev->irq; in iommu_init_intcapxt()
2092 ret = irq_set_affinity_notifier(iommu->dev->irq, notify); in iommu_init_intcapxt()
2095 iommu->devid, iommu->dev->irq); in iommu_init_intcapxt()
2099 iommu_update_intcapxt(iommu); in iommu_init_intcapxt()
2100 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); in iommu_init_intcapxt()
2104 static int iommu_init_msi(struct amd_iommu *iommu) in iommu_init_msi() argument
2108 if (iommu->int_enabled) in iommu_init_msi()
2111 if (iommu->dev->msi_cap) in iommu_init_msi()
2112 ret = iommu_setup_msi(iommu); in iommu_init_msi()
2120 ret = iommu_init_intcapxt(iommu); in iommu_init_msi()
2124 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_msi()
2126 if (iommu->ppr_log != NULL) in iommu_init_msi()
2127 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); in iommu_init_msi()
2129 iommu_ga_log_enable(iommu); in iommu_init_msi()
2261 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
2263 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
2264 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
2265 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
2267 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
2268 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
2269 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
2271 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
2272 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
2273 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
2275 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
2276 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
2277 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
2280 * make IOMMU memory accesses cache coherent in iommu_init_flags()
2282 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
2285 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
2288 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
2292 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
2294 /* RD890 BIOSes may not have completely reconfigured the iommu */ in iommu_apply_resume_quirks()
2295 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
2299 * First, we need to ensure that the iommu is enabled. This is in iommu_apply_resume_quirks()
2307 /* Enable the iommu */ in iommu_apply_resume_quirks()
2311 /* Restore the iommu BAR */ in iommu_apply_resume_quirks()
2312 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2313 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
2314 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
2315 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
2320 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
2324 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
2327 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2328 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
2331 static void iommu_enable_ga(struct amd_iommu *iommu) in iommu_enable_ga() argument
2336 iommu_feature_enable(iommu, CONTROL_GAM_EN); in iommu_enable_ga()
2339 iommu_feature_enable(iommu, CONTROL_GA_EN); in iommu_enable_ga()
2340 iommu->irte_ops = &irte_128_ops; in iommu_enable_ga()
2343 iommu->irte_ops = &irte_32_ops; in iommu_enable_ga()
2349 static void early_enable_iommu(struct amd_iommu *iommu) in early_enable_iommu() argument
2351 iommu_disable(iommu); in early_enable_iommu()
2352 iommu_init_flags(iommu); in early_enable_iommu()
2353 iommu_set_device_table(iommu); in early_enable_iommu()
2354 iommu_enable_command_buffer(iommu); in early_enable_iommu()
2355 iommu_enable_event_buffer(iommu); in early_enable_iommu()
2356 iommu_set_exclusion_range(iommu); in early_enable_iommu()
2357 iommu_enable_ga(iommu); in early_enable_iommu()
2358 iommu_enable_xt(iommu); in early_enable_iommu()
2359 iommu_enable(iommu); in early_enable_iommu()
2360 iommu_flush_all_caches(iommu); in early_enable_iommu()
2373 struct amd_iommu *iommu; in early_enable_iommus() local
2388 for_each_iommu(iommu) { in early_enable_iommus()
2389 clear_translation_pre_enabled(iommu); in early_enable_iommus()
2390 early_enable_iommu(iommu); in early_enable_iommus()
2397 for_each_iommu(iommu) { in early_enable_iommus()
2398 iommu_disable_command_buffer(iommu); in early_enable_iommus()
2399 iommu_disable_event_buffer(iommu); in early_enable_iommus()
2400 iommu_enable_command_buffer(iommu); in early_enable_iommus()
2401 iommu_enable_event_buffer(iommu); in early_enable_iommus()
2402 iommu_enable_ga(iommu); in early_enable_iommus()
2403 iommu_enable_xt(iommu); in early_enable_iommus()
2404 iommu_set_device_table(iommu); in early_enable_iommus()
2405 iommu_flush_all_caches(iommu); in early_enable_iommus()
2425 struct amd_iommu *iommu; in enable_iommus_v2() local
2427 for_each_iommu(iommu) { in enable_iommus_v2()
2428 iommu_enable_ppr_log(iommu); in enable_iommus_v2()
2429 iommu_enable_gt(iommu); in enable_iommus_v2()
2442 struct amd_iommu *iommu; in disable_iommus() local
2444 for_each_iommu(iommu) in disable_iommus()
2445 iommu_disable(iommu); in disable_iommus()
2460 struct amd_iommu *iommu; in amd_iommu_resume() local
2462 for_each_iommu(iommu) in amd_iommu_resume()
2463 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
2576 * This is the hardware init function for AMD IOMMU in the system.
2580 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2657 * IOMMU see for that device in early_amd_iommu_init()
2664 /* IOMMU rlookup table - find the IOMMU for a specific device */ in early_amd_iommu_init()
2697 /* Disable IOMMU if there's Stoney Ridge graphics */ in early_amd_iommu_init()
2701 pr_info("Disable IOMMU on Stoney Ridge\n"); in early_amd_iommu_init()
2757 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
2760 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
2761 ret = iommu_init_msi(iommu); in amd_iommu_enable_interrupts()
2794 * AMD IOMMU Initialization State Machine
2815 pr_info("AMD IOMMU disabled\n"); in state_next()
2862 struct amd_iommu *iommu; in state_next() local
2865 for_each_iommu(iommu) in state_next()
2866 iommu_flush_all_caches(iommu); in state_next()
2932 * This is the core init function for AMD IOMMU hardware in the system.
2938 struct amd_iommu *iommu; in amd_iommu_init() local
2945 * We failed to initialize the AMD IOMMU - try fallback in amd_iommu_init()
2952 for_each_iommu(iommu) in amd_iommu_init()
2953 amd_iommu_debugfs_setup(iommu); in amd_iommu_init()
2971 pr_notice("IOMMU not currently supported when SME is active\n"); in amd_iommu_sme_check()
2978 * Early detect code. This code runs at IOMMU detection time in the DMA
2999 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()
3006 * Parsing functions for the AMD IOMMU specific kernel command line
3160 struct amd_iommu *iommu; in get_amd_iommu() local
3162 for_each_iommu(iommu) in get_amd_iommu()
3164 return iommu; in get_amd_iommu()
3171 * IOMMU EFR Performance Counter support functionality. This code allows
3172 * access to the IOMMU PC functionality.
3178 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_banks() local
3180 if (iommu) in amd_iommu_pc_get_max_banks()
3181 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3195 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_counters() local
3197 if (iommu) in amd_iommu_pc_get_max_counters()
3198 return iommu->max_counters; in amd_iommu_pc_get_max_counters()
3204 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, in iommu_pc_get_set_reg() argument
3210 /* Make sure the IOMMU PC resource is available */ in iommu_pc_get_set_reg()
3214 /* Check for valid iommu and pc register indexing */ in iommu_pc_get_set_reg()
3215 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) in iommu_pc_get_set_reg()
3221 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()
3222 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg()
3230 writel((u32)val, iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3231 writel((val >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3233 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3235 *value |= readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3242 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_get_reg() argument
3244 if (!iommu) in amd_iommu_pc_get_reg()
3247 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); in amd_iommu_pc_get_reg()
3251 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_set_reg() argument
3253 if (!iommu) in amd_iommu_pc_set_reg()
3256 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); in amd_iommu_pc_set_reg()