Lines Matching +full:bypass +full:- +full:enable
1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
6 # The IOASID library may also be used by non-IOMMU_API users
27 Enable this option to impose a limit on the alignment of IOVAs.
67 Enable support for the ARM long descriptor pagetable format.
69 sizes at both stage-1 and stage-2, as well as address spaces
70 up to 48-bits in size.
76 Enable self-tests for LPAE page table allocator. This performs
77 a series of page-table consistency checks during boot.
86 Enable support for the ARM Short-descriptor pagetable format.
87 This supports 32-bit virtual and physical addresses mapped using
88 2-level tables with 4KB pages/1MB sections, and contiguous entries
95 Enable self-tests for ARMv7s page table allocator. This performs
96 a series of page-table consistency checks during boot.
108 at initialization time, cause the IOMMU code to create a top-level
116 Enable passthrough by default, removing the need to pass in
127 # IOMMU-agnostic DMA-mapping layer
170 Supports Interrupt remapping for IO-APIC and MSI devices.
238 depends on !CPU_BIG_ENDIAN # revisit driver if we can enable big-endian ptes
244 non-linear physical memory chunks as linear memory in their
259 bool "Renesas VMSA-compatible IPMMU"
265 Support for the Renesas VMSA-compatible IPMMU found in the R-Mobile
266 APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
294 bool "Support the legacy \"mmu-masters\" devicetree bindings"
297 Support for the badly designed and deprecated "mmu-masters"
306 bool "Default to disabling bypass on ARM SMMU v1 and v2"
310 Say Y here to (by default) disable bypass streams such that
316 introduced would default to _allowing_ bypass (AKA the
320 There are few reasons to allow unmatched stream bypass, and
324 hardcode the bypass disable in the code.
327 'arm-smmu.disable_bypass' will continue to override this
418 bool "Hyper-V x2APIC IRQ Handling"
423 Stub IOMMU driver to handle IRQs as to allow Hyper-V Linux
433 Para-virtualised IOMMU driver with virtio.