122 #define PWM_REG_INTSTS(n)		((3 - (n)) * 0x10 + 0x10)  argument
123 #define PWM_REG_INT_EN(n)		((3 - (n)) * 0x10 + 0x14)  argument
124 #define RK_PWM_VERSION_ID(n)		((3 - (n)) * 0x10 + 0x2c)  argument
125 #define PWM_REG_PWRMATCH_CTRL(n)	((3 - (n)) * 0x10 + 0x50)  argument
126 #define PWM_REG_PWRMATCH_LPRE(n)	((3 - (n)) * 0x10 + 0x54)  argument
127 #define PWM_REG_PWRMATCH_HPRE(n)	((3 - (n)) * 0x10 + 0x58)  argument
128 #define PWM_REG_PWRMATCH_LD(n)		((3 - (n)) * 0x10 + 0x5C)  argument
129 #define PWM_REG_PWRMATCH_HD_ZERO(n)	((3 - (n)) * 0x10 + 0x60)  argument
130 #define PWM_REG_PWRMATCH_HD_ONE(n)	((3 - (n)) * 0x10 + 0x64)  argument
131 #define PWM_PWRMATCH_VALUE(n)		((3 - (n)) * 0x10 + 0x68)  argument
132 #define PWM_PWRCAPTURE_VALUE(n)		((3 - (n)) * 0x10 + 0x9c)  argument
134 #define PWM_CH_INT(n)			BIT(n)  argument
135 #define PWM_CH_POL(n)			BIT(n+8)  argument
137 #define PWM_CH_INT_ENABLE(n)		BIT(n)  argument