Lines Matching refs:cspec
902 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg()
904 return readq(&dd->cspec->cregbase[regno]); in read_7322_creg()
911 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg32()
913 return readl(&dd->cspec->cregbase[regno]); in read_7322_creg32()
1521 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) in qib_7322_sdma_sendctrl()
1666 errs &= dd->cspec->errormask; in handle_7322_errors()
1667 msg = dd->cspec->emsgbuf; in handle_7322_errors()
1672 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); in handle_7322_errors()
1694 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask, in handle_7322_errors()
1741 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_error_tasklet()
1804 if (!ppd->dd->cspec->r1) in handle_serdes_issues()
1825 if (!ppd->dd->cspec->r1 && in handle_serdes_issues()
1840 ppd->dd->cspec->r1 ? in handle_serdes_issues()
2018 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); in qib_7322_set_intr_state()
2021 if (dd->cspec->num_msix_entries) { in qib_7322_set_intr_state()
2074 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_7322_clear_freeze()
2118 hwerrs &= dd->cspec->hwerrmask; in qib_7322_handle_hwerrors()
2133 dd->cspec->stay_in_freeze) { in qib_7322_handle_hwerrors()
2153 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); in qib_7322_handle_hwerrors()
2154 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_handle_hwerrors()
2225 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_init_hwerrors()
2231 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); in qib_7322_init_hwerrors()
2248 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2250 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2251 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_set_7322_armlaunch()
2501 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2504 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2532 if (ppd->dd->cspec->r1) in qib_7322_mini_quiet_serdes()
2642 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2643 extctl = dd->cspec->extctrl & (ppd->port == 1 ? in qib_setup_7322_setextled()
2657 dd->cspec->extctrl = extctl; in qib_setup_7322_setextled()
2658 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_setup_7322_setextled()
2659 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2683 dd->cspec->dca_ctrl = 0; in qib_7322_notify_dca()
2685 dd->cspec->dca_ctrl); in qib_7322_notify_dca()
2695 struct qib_chip_specific *cspec = dd->cspec; in qib_update_rhdrq_dca() local
2699 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) { in qib_update_rhdrq_dca()
2702 cspec->rhdr_cpu[rcd->ctxt] = cpu; in qib_update_rhdrq_dca()
2704 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask; in qib_update_rhdrq_dca()
2705 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |= in qib_update_rhdrq_dca()
2709 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); in qib_update_rhdrq_dca()
2711 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); in qib_update_rhdrq_dca()
2712 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable); in qib_update_rhdrq_dca()
2713 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_rhdrq_dca()
2720 struct qib_chip_specific *cspec = dd->cspec; in qib_update_sdma_dca() local
2725 if (cspec->sdma_cpu[pidx] != cpu) { in qib_update_sdma_dca()
2726 cspec->sdma_cpu[pidx] = cpu; in qib_update_sdma_dca()
2727 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ? in qib_update_sdma_dca()
2730 cspec->dca_rcvhdr_ctrl[4] |= in qib_update_sdma_dca()
2737 (long long) cspec->dca_rcvhdr_ctrl[4]); in qib_update_sdma_dca()
2739 cspec->dca_rcvhdr_ctrl[4]); in qib_update_sdma_dca()
2740 cspec->dca_ctrl |= ppd->hw_pidx ? in qib_update_sdma_dca()
2743 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_sdma_dca()
2749 struct qib_chip_specific *cspec = dd->cspec; in qib_setup_dca() local
2752 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++) in qib_setup_dca()
2753 cspec->rhdr_cpu[i] = -1; in qib_setup_dca()
2754 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) in qib_setup_dca()
2755 cspec->sdma_cpu[i] = -1; in qib_setup_dca()
2756 cspec->dca_rcvhdr_ctrl[0] = in qib_setup_dca()
2761 cspec->dca_rcvhdr_ctrl[1] = in qib_setup_dca()
2766 cspec->dca_rcvhdr_ctrl[2] = in qib_setup_dca()
2771 cspec->dca_rcvhdr_ctrl[3] = in qib_setup_dca()
2776 cspec->dca_rcvhdr_ctrl[4] = in qib_setup_dca()
2779 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) in qib_setup_dca()
2781 cspec->dca_rcvhdr_ctrl[i]); in qib_setup_dca()
2782 for (i = 0; i < cspec->num_msix_entries; i++) in qib_setup_dca()
2830 dd->cspec->main_int_mask = ~0ULL; in qib_7322_free_irq()
2832 for (i = 0; i < dd->cspec->num_msix_entries; i++) { in qib_7322_free_irq()
2834 if (dd->cspec->msix_entries[i].arg) { in qib_7322_free_irq()
2840 free_cpumask_var(dd->cspec->msix_entries[i].mask); in qib_7322_free_irq()
2842 dd->cspec->msix_entries[i].arg); in qib_7322_free_irq()
2847 if (!dd->cspec->num_msix_entries) in qib_7322_free_irq()
2850 dd->cspec->num_msix_entries = 0; in qib_7322_free_irq()
2868 dd->cspec->dca_ctrl = 0; in qib_setup_7322_cleanup()
2869 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl); in qib_setup_7322_cleanup()
2874 kfree(dd->cspec->cntrs); in qib_setup_7322_cleanup()
2875 kfree(dd->cspec->sendchkenable); in qib_setup_7322_cleanup()
2876 kfree(dd->cspec->sendgrhchk); in qib_setup_7322_cleanup()
2877 kfree(dd->cspec->sendibchk); in qib_setup_7322_cleanup()
2878 kfree(dd->cspec->msix_entries); in qib_setup_7322_cleanup()
2886 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2887 dd->cspec->gpio_mask &= ~mask; in qib_setup_7322_cleanup()
2888 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_setup_7322_cleanup()
2889 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2946 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); in unknown_7322_ibits()
2987 if (gpiostatus & dd->cspec->gpio_mask & mask) { in unknown_7322_gpio_intr()
3009 dd->cspec->gpio_mask &= ~gpio_irq; in unknown_7322_gpio_intr()
3010 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in unknown_7322_gpio_intr()
3041 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; in adjust_rcv_timeout()
3054 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; in adjust_rcv_timeout()
3097 istat &= dd->cspec->main_int_mask; in qib_7322intr()
3328 if (!dd->cspec->msix_entries[msixnum].dca) in reset_dca_notifier()
3334 dd->cspec->msix_entries[msixnum].notifier = NULL; in reset_dca_notifier()
3339 struct qib_msix_entry *m = &dd->cspec->msix_entries[msixnum]; in setup_dca_notifier()
3407 if (!dd->cspec->num_msix_entries) { in qib_setup_7322_interrupt()
3419 dd->cspec->main_int_mask = ~0ULL; in qib_setup_7322_interrupt()
3440 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { in qib_setup_7322_interrupt()
3500 dd->cspec->msix_entries[msixnum].arg = arg; in qib_setup_7322_interrupt()
3502 dd->cspec->msix_entries[msixnum].dca = dca; in qib_setup_7322_interrupt()
3503 dd->cspec->msix_entries[msixnum].rcv = in qib_setup_7322_interrupt()
3517 &dd->cspec->msix_entries[msixnum].mask, in qib_setup_7322_interrupt()
3521 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3528 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3532 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3539 dd->cspec->main_int_mask = mask; in qib_setup_7322_interrupt()
3639 msix_entries = dd->cspec->num_msix_entries; in qib_do_7322_reset()
3648 msix_vecsave = kmalloc_array(2 * dd->cspec->num_msix_entries, in qib_do_7322_reset()
3741 dd->cspec->num_msix_entries = msix_entries; in qib_do_7322_reset()
3876 if (rcd->dd->cspec->r1) in qib_7322_get_base_info()
3902 dd->cspec->numctxts = nchipctxts; in qib_7322_config_ctxts()
3935 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
3950 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
3953 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); in qib_7322_config_ctxts()
3955 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); in qib_7322_config_ctxts()
3957 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt, in qib_7322_config_ctxts()
4301 if (ppd->dd->cspec->r1) { in qib_7322_set_ib_cfg()
4487 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4589 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
5001 dd->cspec->ncntrs = i; in init_7322_cntrnames()
5004 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; in init_7322_cntrnames()
5006 dd->cspec->cntrnamelen = 1 + s - cntr7322names; in init_7322_cntrnames()
5007 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64), in init_7322_cntrnames()
5012 dd->cspec->nportcntrs = i - 1; in init_7322_cntrnames()
5013 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; in init_7322_cntrnames()
5016 kmalloc_array(dd->cspec->nportcntrs, sizeof(u64), in init_7322_cntrnames()
5027 ret = dd->cspec->cntrnamelen; in qib_read_7322cntrs()
5033 u64 *cntr = dd->cspec->cntrs; in qib_read_7322cntrs()
5036 ret = dd->cspec->ncntrs * sizeof(u64); in qib_read_7322cntrs()
5043 for (i = 0; i < dd->cspec->ncntrs; i++) in qib_read_7322cntrs()
5062 ret = dd->cspec->portcntrnamelen; in qib_read_7322portcntrs()
5072 ret = dd->cspec->nportcntrs * sizeof(u64); in qib_read_7322portcntrs()
5079 for (i = 0; i < dd->cspec->nportcntrs; i++) { in qib_read_7322portcntrs()
5148 ppd->dd->cspec->r1 ? in qib_get_7322_faststats()
5162 if (!dd->cspec->num_msix_entries) in qib_7322_intr_fallback()
5193 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); in qib_7322_mini_pcs_reset()
5205 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_mini_pcs_reset()
5651 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) in qib_7322_ib_updown()
5703 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5704 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5705 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5706 new_out = (dd->cspec->gpio_out & ~mask) | out; in gpio_7322_mod()
5708 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in gpio_7322_mod()
5710 dd->cspec->gpio_out = new_out; in gpio_7322_mod()
5711 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5802 dd->cspec->cregbase = (u64 __iomem *)(cregbase + in qib_7322_set_baseaddrs()
5978 if (!ret && !ppd->dd->cspec->r1) { in qsfp_7322_event()
6026 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6027 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); in qib_init_7322_qsfp()
6028 dd->cspec->gpio_mask |= mod_prs_bit; in qib_init_7322_qsfp()
6029 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_init_7322_qsfp()
6030 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_init_7322_qsfp()
6031 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6270 if (ppd->dd->cspec->r1) in write_7322_init_portregs()
6301 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6303 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6339 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; in write_7322_initregs()
6379 dd->cspec = (struct qib_chip_specific *)(ppd + 2); in qib_init_7322_variables()
6381 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); in qib_init_7322_variables()
6386 spin_lock_init(&dd->cspec->rcvmod_lock); in qib_init_7322_variables()
6387 spin_lock_init(&dd->cspec->gpio_lock); in qib_init_7322_variables()
6402 dd->cspec->r1 = dd->minrev == 1; in qib_init_7322_variables()
6411 dd->cspec->sendchkenable = in qib_init_7322_variables()
6412 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendchkenable), in qib_init_7322_variables()
6414 dd->cspec->sendgrhchk = in qib_init_7322_variables()
6415 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendgrhchk), in qib_init_7322_variables()
6417 dd->cspec->sendibchk = in qib_init_7322_variables()
6418 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendibchk), in qib_init_7322_variables()
6420 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || in qib_init_7322_variables()
6421 !dd->cspec->sendibchk) { in qib_init_7322_variables()
6453 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; in qib_init_7322_variables()
6455 dd->cspec->hwerrmask = ~0ULL; in qib_init_7322_variables()
6458 dd->cspec->hwerrmask &= in qib_init_7322_variables()
6476 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6480 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6491 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6495 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6556 if (ppd->dd->cspec->r1) in qib_init_7322_variables()
6665 dd->cspec->sdmabufcnt = dd->piobcnt4k; in qib_init_7322_variables()
6668 dd->cspec->sdmabufcnt = 0; in qib_init_7322_variables()
6671 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - in qib_init_7322_variables()
6672 dd->cspec->sdmabufcnt; in qib_init_7322_variables()
6673 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; in qib_init_7322_variables()
6674 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ in qib_init_7322_variables()
6675 dd->last_pio = dd->cspec->lastbuf_for_pio; in qib_init_7322_variables()
6687 dd->cspec->updthresh_dflt = updthresh; in qib_init_7322_variables()
6688 dd->cspec->updthresh = updthresh; in qib_init_7322_variables()
6719 last = dd->cspec->lastbuf_for_pio; in qib_7322_getsendbuf()
6886 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ in init_sdma_7322_regs()
6888 n = dd->cspec->sdmabufcnt; /* failsafe for init */ in init_sdma_7322_regs()
6891 dd->cspec->sdmabufcnt); in init_sdma_7322_regs()
7016 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; in qib_7322_init_ctxt()
7077 clear_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7089 set_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7095 set_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7096 clear_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7101 dd->cspec->updthresh != dd->cspec->updthresh_dflt in qib_7322_txchk_change()
7105 < dd->cspec->updthresh_dflt) in qib_7322_txchk_change()
7110 dd->cspec->updthresh = dd->cspec->updthresh_dflt; in qib_7322_txchk_change()
7112 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7123 clear_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7124 set_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7128 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { in qib_7322_txchk_change()
7129 dd->cspec->updthresh = (rcd->piocnt / in qib_7322_txchk_change()
7132 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7147 dd->cspec->sendchkenable[i]); in qib_7322_txchk_change()
7151 dd->cspec->sendgrhchk[i]); in qib_7322_txchk_change()
7153 dd->cspec->sendibchk[i]); in qib_7322_txchk_change()
7290 dd->cspec->msix_entries = kcalloc(tabsize, in qib_init_iba7322_funcs()
7293 if (!dd->cspec->msix_entries) in qib_init_iba7322_funcs()
7300 dd->cspec->num_msix_entries = tabsize; in qib_init_iba7322_funcs()
7841 if (ppd->dd->cspec->r1) in serdes_7322_init()
7916 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_old()
7926 ppd->dd->cspec->r1 ? in serdes_7322_init_old()
7936 if (!ppd->dd->cspec->r1) { in serdes_7322_init_old()
7996 if (!ppd->dd->cspec->r1) { in serdes_7322_init_new()
8096 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_new()
8117 ppd->dd->cspec->r1 ? in serdes_7322_init_new()
8232 if (!ppd->dd->cspec->r1) in force_h1()
8433 if (!ppd->dd->cspec->r1) in setup_7322_link_recovery()
8436 dd->cspec->recovery_ports_initted++; in setup_7322_link_recovery()
8439 if (!both && dd->cspec->recovery_ports_initted == 1) { in setup_7322_link_recovery()
8467 if (dd->cspec->recovery_ports_initted != 1) in check_7322_rxe_status()
8480 ppd->dd->cspec->stay_in_freeze = 1; in check_7322_rxe_status()