943 				  struct mlx5_umr_wr *umrwr)  in mlx5_ib_post_send_wait()  argument
951 	umrwr->wr.wr_cqe = &umr_context.cqe;  in mlx5_ib_post_send_wait()
954 	err = ib_post_send(umrc->qp, &umrwr->wr, &bad);  in mlx5_ib_post_send_wait()
1479 	struct mlx5_umr_wr umrwr = {};  in mlx5_mr_cache_invalidate()  local
1484 	umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR |  in mlx5_mr_cache_invalidate()
1486 	umrwr.wr.opcode = MLX5_IB_WR_UMR;  in mlx5_mr_cache_invalidate()
1487 	umrwr.pd = mr->dev->umrc.pd;  in mlx5_mr_cache_invalidate()
1488 	umrwr.mkey = mr->mmkey.key;  in mlx5_mr_cache_invalidate()
1489 	umrwr.ignore_free_state = 1;  in mlx5_mr_cache_invalidate()
1491 	return mlx5_ib_post_send_wait(mr->dev, &umrwr);  in mlx5_mr_cache_invalidate()
1498 	struct mlx5_umr_wr umrwr = {};  in rereg_umr()  local
1501 	umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE;  in rereg_umr()
1503 	umrwr.wr.opcode = MLX5_IB_WR_UMR;  in rereg_umr()
1504 	umrwr.mkey = mr->mmkey.key;  in rereg_umr()
1507 		umrwr.pd = pd;  in rereg_umr()
1508 		umrwr.access_flags = access_flags;  in rereg_umr()
1509 		umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;  in rereg_umr()
1512 	err = mlx5_ib_post_send_wait(dev, &umrwr);  in rereg_umr()