Lines Matching refs:write_csr
1362 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) in write_csr() function
1399 write_csr(dd, csr, value); in read_write_csr()
5724 write_csr(dd, SEND_EGRESS_ERR_INFO, info); in handle_send_egress_err_info()
6140 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6176 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6231 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_host_lcb_access()
6242 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_8051_lcb_access()
6365 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, in hreq_response()
6387 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); in handle_8051_request()
6408 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); in handle_8051_request()
6414 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); in handle_8051_request()
6442 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_up_vau()
6463 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_up_vl15()
6465 write_csr(dd, SEND_CM_CREDIT_VL15, (u64)vl15buf in set_up_vl15()
6479 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); in reset_link_credits()
6480 write_csr(dd, SEND_CM_CREDIT_VL15, 0); in reset_link_credits()
6481 write_csr(dd, SEND_CM_GLOBAL_CREDIT, 0); in reset_link_credits()
6520 write_csr(dd, DC_LCB_CFG_RUN, 0); in lcb_shutdown()
6522 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, in lcb_shutdown()
6527 write_csr(dd, DCC_CFG_RESET, reg | in lcb_shutdown()
6532 write_csr(dd, DCC_CFG_RESET, reg); in lcb_shutdown()
6533 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); in lcb_shutdown()
6562 write_csr(dd, DC_DC8051_CFG_RST, 0x1); in _dc_shutdown()
6586 write_csr(dd, DC_DC8051_CFG_RST, 0ull); in _dc_start()
6593 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_OUT_OF_RESET); in _dc_start()
6595 write_csr(dd, DC_LCB_ERR_EN, dd->lcb_err_en); in _dc_start()
6673 write_csr(dd, DC_LCB_CFG_LN_DCLK, 1ull); in adjust_lcb_for_fpga_serdes()
6684 write_csr(dd, DC_LCB_CFG_RX_FIFOS_RADR, rx_radr); in adjust_lcb_for_fpga_serdes()
6686 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, in adjust_lcb_for_fpga_serdes()
6688 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RADR, tx_radr); in adjust_lcb_for_fpga_serdes()
6761 write_csr(dd, RCV_CTRL, rcvctrl); in adjust_rcvctrl()
6786 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); in start_freeze_handling()
6935 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); in handle_freeze()
6939 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK); in handle_freeze()
6941 write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK); in handle_freeze()
7539 write_csr(dd, DC_LCB_CFG_CRC_MODE, in handle_verify_cap()
7545 write_csr(dd, SEND_CM_CTRL, in handle_verify_cap()
7548 write_csr(dd, SEND_CM_CTRL, in handle_verify_cap()
7609 write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); in handle_verify_cap()
7613 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); in handle_verify_cap()
7616 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ in handle_verify_cap()
7884 write_csr(dd, DC_DC8051_ERR_EN, in handle_8051_interrupt()
8347 write_csr(dd, CCE_INT_CLEAR + (8 * i), regs[i]); in general_interrupt()
8380 write_csr(dd, in sdma_interrupt()
8403 write_csr(dd, addr, rcd->imask); in clear_recv_intr()
8411 write_csr(rcd->dd, CCE_INT_FORCE + (8 * rcd->ireg), rcd->imask); in force_recv_intr()
8604 write_csr(dd, DCC_CFG_PORT_CONFIG, reg); in set_logical_state()
8712 write_csr(dd, addr, data); in write_lcb_via_8051()
8742 write_csr(dd, addr, data); in write_lcb_csr()
8815 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); in do_8051_command()
8826 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); in do_8051_command()
8828 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); in do_8051_command()
8865 write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, 0); in do_8051_command()
9239 write_csr(dd, DC_LCB_CFG_LOOPBACK, in do_quick_linkup()
9241 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); in do_quick_linkup()
9246 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); in do_quick_linkup()
9251 write_csr(dd, DC_LCB_CFG_RUN, in do_quick_linkup()
9258 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, in do_quick_linkup()
9276 write_csr(dd, DC_LCB_ERR_EN, 0); /* mask LCB errors */ in do_quick_linkup()
9291 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ in do_quick_linkup()
9309 write_csr(dd, DC_DC8051_CFG_MODE, in init_loopback()
9551 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, in set_qsfp_int_n()
9557 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); in set_qsfp_int_n()
9574 write_csr(dd, in reset_qsfp()
9580 write_csr(dd, in reset_qsfp()
9768 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_CLEAR : ASIC_QSFP1_CLEAR, in init_qsfp_int()
9770 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, in init_qsfp_int()
9778 write_csr(dd, in init_qsfp_int()
9801 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x01); in init_lcb()
9802 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0x00); in init_lcb()
9803 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0x00); in init_lcb()
9804 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); in init_lcb()
9805 write_csr(dd, DC_LCB_CFG_CLK_CNTR, 0x08); in init_lcb()
9806 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x02); in init_lcb()
9807 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0x00); in init_lcb()
10179 write_csr(dd, SEND_LEN_CHECK0, len1); in set_send_length()
10180 write_csr(dd, SEND_LEN_CHECK1, len2); in set_send_length()
10206 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG, len1); in set_send_length()
10229 write_csr(ppd->dd, DCC_CFG_PORT_CONFIG1, c1); in set_lidlmc()
10408 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); in force_logical_link_state_down()
10409 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, in force_logical_link_state_down()
10412 write_csr(dd, DC_LCB_CFG_LANE_WIDTH, 0); in force_logical_link_state_down()
10413 write_csr(dd, DC_LCB_CFG_REINIT_AS_SLAVE, 0); in force_logical_link_state_down()
10414 write_csr(dd, DC_LCB_CFG_CNT_FOR_SKIP_STALL, 0x110); in force_logical_link_state_down()
10415 write_csr(dd, DC_LCB_CFG_LOOPBACK, 0x2); in force_logical_link_state_down()
10417 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 0); in force_logical_link_state_down()
10420 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 1); in force_logical_link_state_down()
10421 write_csr(dd, DC_LCB_CFG_RUN, 1ull << DC_LCB_CFG_RUN_EN_SHIFT); in force_logical_link_state_down()
10428 write_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET, 1); in force_logical_link_state_down()
10429 write_csr(dd, DC_LCB_CFG_ALLOW_LINK_UP, 0); in force_logical_link_state_down()
10430 write_csr(dd, DC_LCB_CFG_IGNORE_LOST_RCLK, 0); in force_logical_link_state_down()
10505 write_csr(dd, DC_LCB_ERR_EN, ~0ull); /* watch LCB errors */ in goto_offline()
10861 write_csr(dd, DCC_CFG_LED_CNTRL, 0); in set_link_state()
11025 write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); in hfi1_set_ib_cfg()
11197 write_csr(dd, target + (i * 8), reg); in set_vl_weights()
11293 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, in set_sc2vlnt()
11311 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, in set_sc2vlnt()
11347 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_global_shared()
11358 write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); in set_global_limit()
11375 write_csr(dd, addr, reg); in set_vl_shared()
11392 write_csr(dd, addr, reg); in set_vl_dedicated()
12115 write_csr(dd, RCV_VL15, HFI1_CTRL_CTXT); in hfi1_rcvctrl()
12118 write_csr(dd, RCV_VL15, 0); in hfi1_rcvctrl()
13233 write_csr(dd, CCE_INT_MASK + (8 * idx), reg); in read_mod_write()
13280 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~(u64)0); in clear_all_interrupts()
13282 write_csr(dd, CCE_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13283 write_csr(dd, MISC_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13284 write_csr(dd, RCV_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13285 write_csr(dd, SEND_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13286 write_csr(dd, SEND_PIO_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13287 write_csr(dd, SEND_DMA_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13288 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~(u64)0); in clear_all_interrupts()
13294 write_csr(dd, DCC_ERR_FLG_CLR, ~(u64)0); in clear_all_interrupts()
13295 write_csr(dd, DC_LCB_ERR_CLR, ~(u64)0); in clear_all_interrupts()
13296 write_csr(dd, DC_DC8051_ERR_CLR, ~(u64)0); in clear_all_interrupts()
13324 write_csr(dd, CCE_INT_MAP + (8 * m), reg); in remap_intr()
13355 write_csr(dd, CCE_INT_MAP + (8 * i), 0); in reset_interrupts()
13573 write_csr(dd, RCV_PARTITION_KEY + in set_partition_keys()
13597 write_csr(dd, CCE_INT_MAP + (8 * i), 0); in write_uninitialized_csrs_and_memories()
13626 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); in write_uninitialized_csrs_and_memories()
13644 write_csr(dd, CCE_CTRL, ctrl_bits); in clear_cce_status()
13675 write_csr(dd, CCE_SCRATCH + (8 * i), 0); in reset_cce_csrs()
13677 write_csr(dd, CCE_ERR_MASK, 0); in reset_cce_csrs()
13678 write_csr(dd, CCE_ERR_CLEAR, ~0ull); in reset_cce_csrs()
13681 write_csr(dd, CCE_COUNTER_ARRAY32 + (8 * i), 0); in reset_cce_csrs()
13682 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_RESETCSR); in reset_cce_csrs()
13685 write_csr(dd, CCE_MSIX_TABLE_LOWER + (8 * i), 0); in reset_cce_csrs()
13686 write_csr(dd, CCE_MSIX_TABLE_UPPER + (8 * i), in reset_cce_csrs()
13691 write_csr(dd, CCE_MSIX_INT_GRANTED, ~0ull); in reset_cce_csrs()
13692 write_csr(dd, CCE_MSIX_VEC_CLR_WITHOUT_INT, ~0ull); in reset_cce_csrs()
13695 write_csr(dd, CCE_INT_MAP, 0); in reset_cce_csrs()
13698 write_csr(dd, CCE_INT_MASK + (8 * i), 0); in reset_cce_csrs()
13699 write_csr(dd, CCE_INT_CLEAR + (8 * i), ~0ull); in reset_cce_csrs()
13704 write_csr(dd, CCE_INT_COUNTER_ARRAY32 + (8 * i), 0); in reset_cce_csrs()
13713 write_csr(dd, MISC_CFG_RSA_R2 + (8 * i), 0); in reset_misc_csrs()
13714 write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0); in reset_misc_csrs()
13715 write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0); in reset_misc_csrs()
13722 write_csr(dd, MISC_CFG_RSA_CMD, 1); in reset_misc_csrs()
13723 write_csr(dd, MISC_CFG_RSA_MU, 0); in reset_misc_csrs()
13724 write_csr(dd, MISC_CFG_FW_CTRL, 0); in reset_misc_csrs()
13730 write_csr(dd, MISC_ERR_MASK, 0); in reset_misc_csrs()
13731 write_csr(dd, MISC_ERR_CLEAR, ~0ull); in reset_misc_csrs()
13743 write_csr(dd, SEND_CTRL, 0); in reset_txe_csrs()
13749 write_csr(dd, SEND_HIGH_PRIORITY_LIMIT, 0); in reset_txe_csrs()
13752 write_csr(dd, SEND_PIO_ERR_MASK, 0); in reset_txe_csrs()
13753 write_csr(dd, SEND_PIO_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13756 write_csr(dd, SEND_DMA_ERR_MASK, 0); in reset_txe_csrs()
13757 write_csr(dd, SEND_DMA_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13760 write_csr(dd, SEND_EGRESS_ERR_MASK, 0); in reset_txe_csrs()
13761 write_csr(dd, SEND_EGRESS_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13763 write_csr(dd, SEND_BTH_QP, 0); in reset_txe_csrs()
13764 write_csr(dd, SEND_STATIC_RATE_CONTROL, 0); in reset_txe_csrs()
13765 write_csr(dd, SEND_SC2VLT0, 0); in reset_txe_csrs()
13766 write_csr(dd, SEND_SC2VLT1, 0); in reset_txe_csrs()
13767 write_csr(dd, SEND_SC2VLT2, 0); in reset_txe_csrs()
13768 write_csr(dd, SEND_SC2VLT3, 0); in reset_txe_csrs()
13769 write_csr(dd, SEND_LEN_CHECK0, 0); in reset_txe_csrs()
13770 write_csr(dd, SEND_LEN_CHECK1, 0); in reset_txe_csrs()
13772 write_csr(dd, SEND_ERR_MASK, 0); in reset_txe_csrs()
13773 write_csr(dd, SEND_ERR_CLEAR, ~0ull); in reset_txe_csrs()
13776 write_csr(dd, SEND_LOW_PRIORITY_LIST + (8 * i), 0); in reset_txe_csrs()
13778 write_csr(dd, SEND_HIGH_PRIORITY_LIST + (8 * i), 0); in reset_txe_csrs()
13780 write_csr(dd, SEND_CONTEXT_SET_CTRL + (8 * i), 0); in reset_txe_csrs()
13782 write_csr(dd, SEND_COUNTER_ARRAY32 + (8 * i), 0); in reset_txe_csrs()
13784 write_csr(dd, SEND_COUNTER_ARRAY64 + (8 * i), 0); in reset_txe_csrs()
13785 write_csr(dd, SEND_CM_CTRL, SEND_CM_CTRL_RESETCSR); in reset_txe_csrs()
13786 write_csr(dd, SEND_CM_GLOBAL_CREDIT, SEND_CM_GLOBAL_CREDIT_RESETCSR); in reset_txe_csrs()
13788 write_csr(dd, SEND_CM_TIMER_CTRL, 0); in reset_txe_csrs()
13789 write_csr(dd, SEND_CM_LOCAL_AU_TABLE0_TO3, 0); in reset_txe_csrs()
13790 write_csr(dd, SEND_CM_LOCAL_AU_TABLE4_TO7, 0); in reset_txe_csrs()
13791 write_csr(dd, SEND_CM_REMOTE_AU_TABLE0_TO3, 0); in reset_txe_csrs()
13792 write_csr(dd, SEND_CM_REMOTE_AU_TABLE4_TO7, 0); in reset_txe_csrs()
13794 write_csr(dd, SEND_CM_CREDIT_VL + (8 * i), 0); in reset_txe_csrs()
13795 write_csr(dd, SEND_CM_CREDIT_VL15, 0); in reset_txe_csrs()
13800 write_csr(dd, SEND_EGRESS_ERR_INFO, ~0ull); in reset_txe_csrs()
13888 write_csr(dd, RCV_CTRL, RCV_CTRL_RX_RBUF_INIT_SMASK); in init_rbufs()
13925 write_csr(dd, RCV_CTRL, 0); in reset_rxe_csrs()
13931 write_csr(dd, RCV_BTH_QP, 0); in reset_rxe_csrs()
13932 write_csr(dd, RCV_MULTICAST, 0); in reset_rxe_csrs()
13933 write_csr(dd, RCV_BYPASS, 0); in reset_rxe_csrs()
13934 write_csr(dd, RCV_VL15, 0); in reset_rxe_csrs()
13936 write_csr(dd, RCV_ERR_INFO, in reset_rxe_csrs()
13939 write_csr(dd, RCV_ERR_MASK, 0); in reset_rxe_csrs()
13940 write_csr(dd, RCV_ERR_CLEAR, ~0ull); in reset_rxe_csrs()
13943 write_csr(dd, RCV_QP_MAP_TABLE + (8 * i), 0); in reset_rxe_csrs()
13945 write_csr(dd, RCV_PARTITION_KEY + (8 * i), 0); in reset_rxe_csrs()
13947 write_csr(dd, RCV_COUNTER_ARRAY32 + (8 * i), 0); in reset_rxe_csrs()
13949 write_csr(dd, RCV_COUNTER_ARRAY64 + (8 * i), 0); in reset_rxe_csrs()
13953 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), 0); in reset_rxe_csrs()
14003 write_csr(dd, SEND_SC2VLT0, SC2VL_VAL( in init_sc2vl_tables()
14009 write_csr(dd, SEND_SC2VLT1, SC2VL_VAL( in init_sc2vl_tables()
14015 write_csr(dd, SEND_SC2VLT2, SC2VL_VAL( in init_sc2vl_tables()
14021 write_csr(dd, SEND_SC2VLT3, SC2VL_VAL( in init_sc2vl_tables()
14029 write_csr(dd, DCC_CFG_SC_VL_TABLE_15_0, DC_SC_VL_VAL( in init_sc2vl_tables()
14033 write_csr(dd, DCC_CFG_SC_VL_TABLE_31_16, DC_SC_VL_VAL( in init_sc2vl_tables()
14073 write_csr(dd, SEND_CTRL, 0); in init_chip()
14079 write_csr(dd, RCV_CTRL, 0); in init_chip()
14081 write_csr(dd, RCV_CTXT_CTRL, 0); in init_chip()
14084 write_csr(dd, CCE_INT_MASK + (8 * i), 0ull); in init_chip()
14092 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); in init_chip()
14132 write_csr(dd, CCE_DC_CTRL, 0); in init_chip()
14147 write_csr(dd, ASIC_QSFP1_OUT, 0x1f); in init_chip()
14148 write_csr(dd, ASIC_QSFP2_OUT, 0x1f); in init_chip()
14181 write_csr(dd, SEND_BTH_QP, in init_kdeth_qp()
14185 write_csr(dd, RCV_BTH_QP, in init_kdeth_qp()
14235 write_csr(dd, regno, reg); in init_qpmap_table()
14295 write_csr(dd, RCV_RSM_MAP_TABLE + (8 * i), rmt->map[i]); in complete_rsm_map_table()
14314 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), in add_rsm_rule()
14318 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), in add_rsm_rule()
14325 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), in add_rsm_rule()
14337 write_csr(dd, RCV_RSM_CFG + (8 * rule_index), 0); in clear_rsm_rule()
14338 write_csr(dd, RCV_RSM_SELECT + (8 * rule_index), 0); in clear_rsm_rule()
14339 write_csr(dd, RCV_RSM_MATCH + (8 * rule_index), 0); in clear_rsm_rule()
14590 write_csr(dd, regoff, reg); in hfi1_netdev_update_rmt()
14684 write_csr(dd, RCV_ERR_MASK, ~0ull); in init_rxe()
14715 write_csr(dd, RCV_BYPASS, val); in init_rxe()
14722 write_csr(dd, CCE_ERR_MASK, ~0ull); in init_other()
14724 write_csr(dd, MISC_ERR_MASK, DRIVER_MISC_MASK); in init_other()
14726 write_csr(dd, DCC_ERR_FLG_EN, ~0ull); in init_other()
14727 write_csr(dd, DC_DC8051_ERR_EN, ~0ull); in init_other()
14741 write_csr(dd, csr0to3, in assign_cm_au_table()
14748 write_csr(dd, csr4to7, in assign_cm_au_table()
14776 write_csr(dd, SEND_PIO_ERR_MASK, ~0ull); in init_txe()
14777 write_csr(dd, SEND_DMA_ERR_MASK, ~0ull); in init_txe()
14778 write_csr(dd, SEND_ERR_MASK, ~0ull); in init_txe()
14779 write_csr(dd, SEND_EGRESS_ERR_MASK, ~0ull); in init_txe()
14795 write_csr(dd, SEND_CM_TIMER_CTRL, HFI1_CREDIT_RETURN_RATE); in init_txe()
14997 write_csr(dd, CCE_INT_MASK, 0ull); in check_int_registers()
15003 write_csr(dd, CCE_INT_CLEAR, all_bits); in check_int_registers()
15009 write_csr(dd, CCE_INT_FORCE, all_bits); in check_int_registers()
15015 write_csr(dd, CCE_INT_CLEAR, all_bits); in check_int_registers()
15016 write_csr(dd, CCE_INT_MASK, mask); in check_int_registers()
15020 write_csr(dd, CCE_INT_MASK, mask); in check_int_registers()
15447 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); in thermal_init()
15490 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); in thermal_init()