1406 	hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);  in read_write_csr()
1509 	hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);  in dc_access_lcb_cntr()
1559 	hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);  in read_write_sw()
12246 			hfi1_cdbg(CNTR, "reading %s", entry->name);  in hfi1_read_cntrs()
12249 				hfi1_cdbg(CNTR, "\tDisabled\n");  in hfi1_read_cntrs()
12252 					hfi1_cdbg(CNTR, "\tPer VL\n");  in hfi1_read_cntrs()
12259 						   CNTR,  in hfi1_read_cntrs()
12266 					hfi1_cdbg(CNTR,  in hfi1_read_cntrs()
12273 						hfi1_cdbg(CNTR,  in hfi1_read_cntrs()
12284 					hfi1_cdbg(CNTR, "\tRead 0x%llx", val);  in hfi1_read_cntrs()
12312 			hfi1_cdbg(CNTR, "reading %s", entry->name);  in hfi1_read_portcntrs()
12315 				hfi1_cdbg(CNTR, "\tDisabled\n");  in hfi1_read_portcntrs()
12320 				hfi1_cdbg(CNTR, "\tPer VL");  in hfi1_read_portcntrs()
12326 					   CNTR,  in hfi1_read_portcntrs()
12337 				hfi1_cdbg(CNTR, "\tRead 0x%llx", val);  in hfi1_read_portcntrs()
12389 	hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);  in read_dev_port_cntr()
12424 	hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);  in read_dev_port_cntr()
12440 	hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);  in write_dev_port_cntr()
12458 	hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);  in write_dev_port_cntr()
12556 	    CNTR,  in do_update_synth_timer()
12566 		hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",  in do_update_synth_timer()
12570 		hfi1_cdbg(CNTR,  in do_update_synth_timer()
12574 			hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",  in do_update_synth_timer()
12581 		hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);  in do_update_synth_timer()
12618 		hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",  in do_update_synth_timer()
12622 		hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);  in do_update_synth_timer()