27  * Here are the standard PIO mode 0-4 timings for each "format".
28  * Format-0 uses fast data reg timings, with slower command reg timings.
32 	{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
33 	{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
37  * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
39 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
40 #define CS5530_BASEREG(hwif)	(((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
92 	if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {  in cs5530_udma_filter()
97 			mask = 0;  in cs5530_udma_filter()
106 	unsigned int reg, timings = 0;  in cs5530_set_dma_mode()
109 		case XFER_UDMA_0:	timings = 0x00921250; break;  in cs5530_set_dma_mode()
110 		case XFER_UDMA_1:	timings = 0x00911140; break;  in cs5530_set_dma_mode()
111 		case XFER_UDMA_2:	timings = 0x00911030; break;  in cs5530_set_dma_mode()
112 		case XFER_MW_DMA_0:	timings = 0x00077771; break;  in cs5530_set_dma_mode()
113 		case XFER_MW_DMA_1:	timings = 0x00012121; break;  in cs5530_set_dma_mode()
114 		case XFER_MW_DMA_2:	timings = 0x00002020; break;  in cs5530_set_dma_mode()
118 	timings |= reg & 0x80000000;		/* preserve PIO format bit */  in cs5530_set_dma_mode()
119 	if ((drive-> dn & 1) == 0) {		/* are we configuring drive0? */  in cs5530_set_dma_mode()
122 		if (timings & 0x00100000)  in cs5530_set_dma_mode()
123 			reg |=  0x00100000;	/* enable UDMA timings for both drives */  in cs5530_set_dma_mode()
125 			reg &= ~0x00100000;	/* disable UDMA timings for both drives */  in cs5530_set_dma_mode()
142 	if (pci_resource_start(dev, 4) == 0)  in init_chipset_cs5530()
167 	 * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530  in init_chipset_cs5530()
175 	 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530  in init_chipset_cs5530()
178 	pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);  in init_chipset_cs5530()
182 	 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530  in init_chipset_cs5530()
185 	pci_write_config_word(cs5530_0, 0xd0, 0x5006);  in init_chipset_cs5530()
188 	 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:  in init_chipset_cs5530()
193 	pci_write_config_byte(master_0, 0x40, 0x1e);  in init_chipset_cs5530()
197 	 *	   16bytes: set bit-1 at 0x41 (reg value of 0x16)  in init_chipset_cs5530()
198 	 *	all others: clear bit-1 at 0x41, and do:  in init_chipset_cs5530()
199 	 *	  128bytes: OR 0x00 at 0x41  in init_chipset_cs5530()
200 	 *	  256bytes: OR 0x04 at 0x41  in init_chipset_cs5530()
201 	 *	  512bytes: OR 0x08 at 0x41  in init_chipset_cs5530()
202 	 *	 1024bytes: OR 0x0c at 0x41  in init_chipset_cs5530()
205 	pci_write_config_byte(master_0, 0x41, 0x14);  in init_chipset_cs5530()
212 	pci_write_config_byte(master_0, 0x42, 0x00);  in init_chipset_cs5530()
213 	pci_write_config_byte(master_0, 0x43, 0xc1);  in init_chipset_cs5530()
218 	return 0;  in init_chipset_cs5530()
235 	d0_timings = inl(basereg + 0);  in init_hwif_cs5530()
237 		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);  in init_hwif_cs5530()
239 		outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);  in init_hwif_cs5530()
266 	{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
267 	{ 0, },