42 #define STM32F7_I2C_CR2				0x04  macro
774 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
784 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
804 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
807 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
864 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
932 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
948 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1098 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1110 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1182 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1262 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1280 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1426 			cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1428 			writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1431 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_isr_event()
1532 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_isr_event()
1877 	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);  in stm32f7_i2c_reg_slave()
2310 	backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_backup()
2342 	writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_restore()