51 #define STM32F4_I2C_CR2_FREQ_MASK	GENMASK(5, 0)
88 #define STM32F4_I2C_TRISE_VALUE_MASK	GENMASK(5, 0)
200 	 * In standard mode, the maximum allowed SCL rise time is 1000 ns.  in stm32f4_i2c_set_rise_time()
201 	 * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to  in stm32f4_i2c_set_rise_time()
202 	 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be  in stm32f4_i2c_set_rise_time()
203 	 * programmed with 0x9. (1000 ns / 125 ns + 1)  in stm32f4_i2c_set_rise_time()
204 	 * So, for I2C standard mode TRISE = FREQ[5:0] + 1  in stm32f4_i2c_set_rise_time()
206 	 * In fast mode, the maximum allowed SCL rise time is 300 ns.  in stm32f4_i2c_set_rise_time()
207 	 * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to  in stm32f4_i2c_set_rise_time()
208 	 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be  in stm32f4_i2c_set_rise_time()
209 	 * programmed with 0x3. (300 ns / 125 ns + 1)  in stm32f4_i2c_set_rise_time()
210 	 * So, for I2C fast mode TRISE = FREQ[5:0] * 300 / 1000 + 1  in stm32f4_i2c_set_rise_time()
214 	 * and so fits into the TRISE bits [5:0].  in stm32f4_i2c_set_rise_time()
239 		 * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns  in stm32f4_i2c_set_speed_mode()
240 		 * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached  in stm32f4_i2c_set_speed_mode()
257 		 * CCR = 6000000 / (400000 * 3) = 5  in stm32f4_i2c_set_speed_mode()
258 		 * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns  in stm32f4_i2c_set_speed_mode()
259 		 * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns  in stm32f4_i2c_set_speed_mode()
260 		 * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached  in stm32f4_i2c_set_speed_mode()