38 #define S3C2410_IICCON			0x00  macro
192 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_ack()
193 	writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_ack()
200 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_enable_ack()
201 	writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_enable_ack()
209 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_irq()
210 	writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_irq()
217 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_enable_irq()
218 	writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_enable_irq()
226 		if (readl(i2c->regs + S3C2410_IICCON)  in is_ack()
263 	iiccon = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_message_start()
276 	writel(iiccon, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_message_start()
550 	tmp = readl(i2c->regs + S3C2410_IICCON);  in i2c_s3c_irq_nextbyte()
552 	writel(tmp, i2c->regs + S3C2410_IICCON);  in i2c_s3c_irq_nextbyte()
576 		tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_irq()
578 		writel(tmp, i2c->regs +  S3C2410_IICCON);  in s3c24xx_i2c_irq()
611 	tmp = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_bus()
614 	writel(tmp, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_disable_bus()
859 	iiccon = readl(i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_clockrate()
869 	writel(iiccon, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_clockrate()
994 	writel(0, i2c->regs + S3C2410_IICCON);  in s3c24xx_i2c_init()
1008 		readl(i2c->regs + S3C2410_IICCON));  in s3c24xx_i2c_init()