35 #define ICMCR	0x04	/* master ctrl */  macro
166 	return !!(rcar_i2c_read(priv, ICMCR) & FSCL);  in rcar_i2c_get_scl()
179 	rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);  in rcar_i2c_set_scl()
191 	rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);  in rcar_i2c_set_sda()
198 	return !(rcar_i2c_read(priv, ICMCR) & FSDA);  in rcar_i2c_get_bus_free()
213 	rcar_i2c_write(priv, ICMCR, MDBS);  in rcar_i2c_init()
228 	ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10,  in rcar_i2c_bus_barrier()
348 		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);  in rcar_i2c_prepare_msg()
353 			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);  in rcar_i2c_prepare_msg()
517 			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);  in rcar_i2c_irq_send()
550 			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);  in rcar_i2c_irq_recv()
552 			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);  in rcar_i2c_irq_recv()
683 		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);  in rcar_i2c_gen2_irq()
706 		rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);  in rcar_i2c_gen3_irq()