141 #define NPCM_I2CFIF_CTS			0x10 /* Both FIFOs Control and Status */  macro
465 	val = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
467 	iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
653 	iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_reset()
1048 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1073 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1120 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1128 				       ioread8(bus->reg + NPCM_I2CFIF_CTS))) {  in npcm_i2c_int_slave_handler()
1137 		iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1414 				data = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1416 				iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1465 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_nack()
1584 		fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1589 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1593 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1706 	fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
1709 	iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
2052 		i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()
2055 		iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()