97 #define IE_OFFSET                    0x38  macro
320 	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);  in bcm_iproc_i2c_slave_init()
417 	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);  in slave_rx_tasklet_fn()
439 		val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);  in bcm_iproc_i2c_slave_isr()
441 		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);  in bcm_iproc_i2c_slave_isr()
488 		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,  in bcm_iproc_i2c_slave_isr()
562 				tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);  in bcm_iproc_i2c_send()
564 				iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,  in bcm_iproc_i2c_send()
587 			val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);  in bcm_iproc_i2c_read()
589 			iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);  in bcm_iproc_i2c_read()
634 	slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &  in bcm_iproc_i2c_isr()
677 	val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);  in bcm_iproc_i2c_init()
680 	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);  in bcm_iproc_i2c_init()
763 		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);  in bcm_iproc_i2c_xfer_wait()
765 		iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);  in bcm_iproc_i2c_xfer_wait()
929 		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);  in bcm_iproc_i2c_xfer_internal()
1114 		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);  in bcm_iproc_i2c_remove()
1115 		iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);  in bcm_iproc_i2c_remove()
1136 		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);  in bcm_iproc_i2c_suspend()
1137 		iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);  in bcm_iproc_i2c_suspend()
1213 	tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);  in bcm_iproc_i2c_unreg_slave()
1216 	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);  in bcm_iproc_i2c_unreg_slave()