Lines Matching full:dsi
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
550 /* General DSI hardware state. */
568 /* DSI channel for the panel we're connected to. */
575 /* Input clock from CPRMAN to the digital PHY, for the DSI
580 /* Input clock to the analog PHY, used to generate the DSI bit
585 /* HS Clocks generated within the DSI analog PHY. */
604 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) in dsi_dma_workaround_write() argument
606 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
613 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
617 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
620 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
621 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
639 #define DSI_READ(offset) readl(dsi->regs + (offset))
640 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
642 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
644 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
645 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
647 /* VC4 DSI encoder KMS struct */
650 struct vc4_dsi *dsi; member
709 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch) in vc4_dsi_latch_ulps() argument
722 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps) in vc4_dsi_ulps() argument
724 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
727 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
728 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
729 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
732 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
733 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
734 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
737 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
738 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
739 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
751 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
752 "Timeout waiting for DSI ULPS entry: STAT 0x%08x", in vc4_dsi_ulps()
755 vc4_dsi_latch_ulps(dsi, false); in vc4_dsi_ulps()
759 /* The DSI module can't be disabled while the module is in vc4_dsi_ulps()
764 vc4_dsi_latch_ulps(dsi, ulps); in vc4_dsi_ulps()
770 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
771 "Timeout waiting for DSI STOP entry: STAT 0x%08x", in vc4_dsi_ulps()
799 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_disable() local
800 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_disable()
803 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
807 if (iter == dsi->bridge) in vc4_dsi_encoder_disable()
811 vc4_dsi_ulps(dsi, true); in vc4_dsi_encoder_disable()
813 list_for_each_entry_from(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
818 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_encoder_disable()
819 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_encoder_disable()
820 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_encoder_disable()
826 * DSI PLL divider.
830 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
831 * the pixel clock), only has an integer divider off of DSI.
843 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_mode_fixup() local
844 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_encoder_mode_fixup()
847 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_encoder_mode_fixup()
862 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_encoder_mode_fixup()
879 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_enable() local
880 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_enable()
894 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port); in vc4_dsi_encoder_enable()
899 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
900 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); in vc4_dsi_encoder_enable()
901 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
908 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_encoder_enable()
909 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_encoder_enable()
911 dev_err(&dsi->pdev->dev, in vc4_dsi_encoder_enable()
915 /* Reset the DSI and all its fifos. */ in vc4_dsi_encoder_enable()
928 if (dsi->variant->port == 0) { in vc4_dsi_encoder_enable()
932 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
935 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_encoder_enable()
956 if (dsi->lanes < 4) in vc4_dsi_encoder_enable()
958 if (dsi->lanes < 3) in vc4_dsi_encoder_enable()
960 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
973 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_encoder_enable()
975 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret); in vc4_dsi_encoder_enable()
979 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
981 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret); in vc4_dsi_encoder_enable()
985 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
992 * pixel clock for pushing pixels into DSI. in vc4_dsi_encoder_enable()
995 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_encoder_enable()
1001 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_encoder_enable()
1003 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret); in vc4_dsi_encoder_enable()
1007 /* How many ns one DSI unit interval is. Note that the clock in vc4_dsi_encoder_enable()
1071 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_encoder_enable()
1072 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_encoder_enable()
1073 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_encoder_enable()
1075 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_encoder_enable()
1077 (dsi->variant->port == 0 ? in vc4_dsi_encoder_enable()
1103 if (dsi->variant->port == 0) in vc4_dsi_encoder_enable()
1113 vc4_dsi_ulps(dsi, false); in vc4_dsi_encoder_enable()
1115 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1120 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_encoder_enable()
1122 VC4_SET_FIELD(dsi->divider, in vc4_dsi_encoder_enable()
1124 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_encoder_enable()
1135 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1141 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
1142 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); in vc4_dsi_encoder_enable()
1143 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
1150 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_transfer() local
1228 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1229 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1230 if (dsi->variant->port == 0) { in vc4_dsi_host_transfer()
1258 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1260 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1261 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1265 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1282 DRM_ERROR("DSI returned %db, expecting %db\n", in vc4_dsi_host_transfer()
1305 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret); in vc4_dsi_host_transfer()
1321 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_attach() local
1323 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1324 dsi->channel = device->channel; in vc4_dsi_host_attach()
1325 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1329 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1330 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1333 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1334 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1337 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1338 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1341 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1342 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1345 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1346 dsi->format); in vc4_dsi_host_attach()
1350 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1351 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1390 static void dsi_handle_error(struct vc4_dsi *dsi, in dsi_handle_error() argument
1397 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type); in dsi_handle_error()
1409 struct vc4_dsi *dsi = data; in vc4_dsi_irq_defer_to_thread_handler() local
1424 struct vc4_dsi *dsi = data; in vc4_dsi_irq_handler() local
1430 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1432 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1434 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1436 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1438 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1440 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1442 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1444 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1447 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE : in vc4_dsi_irq_handler()
1450 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1453 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1454 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1464 * @dsi: DSI encoder
1467 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi) in vc4_dsi_init_phy_clocks() argument
1469 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1470 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1481 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1482 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1486 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1488 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1491 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1497 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); in vc4_dsi_init_phy_clocks()
1504 * setting both our parent DSI PLL's rate and this in vc4_dsi_init_phy_clocks()
1522 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1527 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1534 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_bind() local
1545 dsi->variant = match->data; in vc4_dsi_bind()
1552 INIT_LIST_HEAD(&dsi->bridge_chain); in vc4_dsi_bind()
1553 vc4_dsi_encoder->base.type = dsi->variant->port ? in vc4_dsi_bind()
1555 vc4_dsi_encoder->dsi = dsi; in vc4_dsi_bind()
1556 dsi->encoder = &vc4_dsi_encoder->base.base; in vc4_dsi_bind()
1558 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1559 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1560 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1562 dsi->regset.base = dsi->regs; in vc4_dsi_bind()
1563 dsi->regset.regs = dsi->variant->regs; in vc4_dsi_bind()
1564 dsi->regset.nregs = dsi->variant->nregs; in vc4_dsi_bind()
1576 if (dsi->variant->broken_axi_workaround) { in vc4_dsi_bind()
1577 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1578 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1580 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1587 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1588 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1589 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1600 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1604 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1610 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1615 "vc4 dsi", dsi); in vc4_dsi_bind()
1618 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); in vc4_dsi_bind()
1625 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1626 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1627 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1633 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1634 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1635 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1641 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1642 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1643 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1650 &panel, &dsi->bridge); in vc4_dsi_bind()
1654 * dev from being registered. Of course that means the DSI in vc4_dsi_bind()
1665 dsi->bridge = devm_drm_panel_bridge_add_typed(dev, panel, in vc4_dsi_bind()
1667 if (IS_ERR(dsi->bridge)) in vc4_dsi_bind()
1668 return PTR_ERR(dsi->bridge); in vc4_dsi_bind()
1672 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1678 ret = vc4_dsi_init_phy_clocks(dsi); in vc4_dsi_bind()
1682 drm_simple_encoder_init(drm, dsi->encoder, DRM_MODE_ENCODER_DSI); in vc4_dsi_bind()
1683 drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs); in vc4_dsi_bind()
1685 ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL, 0); in vc4_dsi_bind()
1695 list_splice_init(&dsi->encoder->bridge_chain, &dsi->bridge_chain); in vc4_dsi_bind()
1697 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset); in vc4_dsi_bind()
1707 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_unbind() local
1709 if (dsi->bridge) in vc4_dsi_unbind()
1716 list_splice_init(&dsi->bridge_chain, &dsi->encoder->bridge_chain); in vc4_dsi_unbind()
1717 drm_encoder_cleanup(dsi->encoder); in vc4_dsi_unbind()
1728 struct vc4_dsi *dsi; in vc4_dsi_dev_probe() local
1731 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in vc4_dsi_dev_probe()
1732 if (!dsi) in vc4_dsi_dev_probe()
1734 dev_set_drvdata(dev, dsi); in vc4_dsi_dev_probe()
1736 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1738 /* Note, the initialization sequence for DSI and panels is in vc4_dsi_dev_probe()
1747 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1748 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1749 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1753 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_probe()
1763 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_dev_remove() local
1766 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()