Lines Matching refs:dc
43 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
48 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
89 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
91 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
114 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
310 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering() local
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
325 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering() local
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
343 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window() local
416 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
522 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
616 struct tegra_dc *dc = to_tegra_dc(state->crtc); in tegra_plane_atomic_check() local
635 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
646 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
782 struct tegra_dc *dc) in tegra_primary_plane_create() argument
799 plane->dc = dc; in tegra_primary_plane_create()
801 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
802 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
803 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
823 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
867 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); in tegra_cursor_atomic_update() local
898 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in tegra_cursor_atomic_update()
902 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in tegra_cursor_atomic_update()
906 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
908 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
910 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
917 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
922 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in tegra_cursor_atomic_update()
928 struct tegra_dc *dc; in tegra_cursor_atomic_disable() local
935 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
937 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
939 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
956 struct tegra_dc *dc) in tegra_dc_cursor_plane_create() argument
976 plane->dc = dc; in tegra_dc_cursor_plane_create()
1073 struct tegra_dc *dc, in tegra_dc_overlay_plane_create() argument
1090 plane->dc = dc; in tegra_dc_overlay_plane_create()
1092 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1093 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1119 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1126 struct tegra_dc *dc) in tegra_dc_add_shared_planes() argument
1131 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1132 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1134 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1138 plane = tegra_shared_plane_create(drm, dc, in tegra_dc_add_shared_planes()
1160 struct tegra_dc *dc) in tegra_dc_add_planes() argument
1167 primary = tegra_primary_plane_create(drm, dc); in tegra_dc_add_planes()
1171 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1177 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, in tegra_dc_add_planes()
1454 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1458 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1460 if (!dc->base.state->active) { in tegra_dc_show_regs()
1469 offset, tegra_dc_readl(dc, offset)); in tegra_dc_show_regs()
1473 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1480 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc() local
1484 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1486 if (!dc->base.state->active) { in tegra_dc_show_crc()
1492 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1493 tegra_dc_commit(dc); in tegra_dc_show_crc()
1495 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1496 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1498 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1501 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1504 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1511 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats() local
1513 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1514 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1515 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1516 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1532 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_late_register() local
1540 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1542 if (!dc->debugfs_files) in tegra_dc_late_register()
1546 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1548 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1557 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_early_unregister() local
1559 drm_debugfs_remove_files(dc->debugfs_files, count, minor); in tegra_dc_early_unregister()
1560 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1561 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1566 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_get_vblank_counter() local
1569 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1570 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1573 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1578 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_enable_vblank() local
1581 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1583 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1590 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_disable_vblank() local
1593 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1595 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1612 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
1619 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1620 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1623 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1628 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1632 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1636 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1639 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1656 int tegra_dc_state_setup_clock(struct tegra_dc *dc, in tegra_dc_state_setup_clock() argument
1663 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1673 static void tegra_dc_commit_state(struct tegra_dc *dc, in tegra_dc_commit_state() argument
1679 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_commit_state()
1681 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_commit_state()
1694 dev_err(dc->dev, in tegra_dc_commit_state()
1698 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_commit_state()
1700 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_commit_state()
1701 dc->clk, state->pclk, err); in tegra_dc_commit_state()
1704 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_commit_state()
1708 if (!dc->soc->has_nvdisplay) { in tegra_dc_commit_state()
1710 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_dc_commit_state()
1714 static void tegra_dc_stop(struct tegra_dc *dc) in tegra_dc_stop() argument
1719 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1721 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1723 tegra_dc_commit(dc); in tegra_dc_stop()
1726 static bool tegra_dc_idle(struct tegra_dc *dc) in tegra_dc_idle() argument
1730 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_idle()
1735 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) in tegra_dc_wait_idle() argument
1740 if (tegra_dc_idle(dc)) in tegra_dc_wait_idle()
1746 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1753 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_disable() local
1757 if (!tegra_dc_idle(dc)) { in tegra_crtc_atomic_disable()
1758 tegra_dc_stop(dc); in tegra_crtc_atomic_disable()
1764 tegra_dc_wait_idle(dc, 100); in tegra_crtc_atomic_disable()
1783 if (dc->rgb) { in tegra_crtc_atomic_disable()
1784 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
1787 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
1790 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
1802 err = host1x_client_suspend(&dc->client); in tegra_crtc_atomic_disable()
1804 dev_err(dc->dev, "failed to suspend: %d\n", err); in tegra_crtc_atomic_disable()
1812 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_enable() local
1816 err = host1x_client_resume(&dc->client); in tegra_crtc_atomic_enable()
1818 dev_err(dc->dev, "failed to resume: %d\n", err); in tegra_crtc_atomic_enable()
1823 if (dc->syncpt) { in tegra_crtc_atomic_enable()
1824 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
1826 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
1832 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_crtc_atomic_enable()
1835 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_crtc_atomic_enable()
1838 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1841 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
1848 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
1852 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
1855 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
1857 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_crtc_atomic_enable()
1861 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
1865 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
1870 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_crtc_atomic_enable()
1874 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_crtc_atomic_enable()
1878 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
1882 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
1885 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
1886 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); in tegra_crtc_atomic_enable()
1888 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_crtc_atomic_enable()
1891 tegra_dc_commit_state(dc, state); in tegra_crtc_atomic_enable()
1894 tegra_dc_set_timings(dc, mode); in tegra_crtc_atomic_enable()
1897 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
1898 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
1900 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
1903 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
1906 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
1908 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1909 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
1912 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
1916 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1918 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); in tegra_crtc_atomic_enable()
1921 tegra_dc_commit(dc); in tegra_crtc_atomic_enable()
1949 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_flush() local
1953 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1954 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1957 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1958 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1970 struct tegra_dc *dc = data; in tegra_dc_irq() local
1973 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
1974 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
1980 dc->stats.frames++; in tegra_dc_irq()
1987 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
1988 dc->stats.vblank++; in tegra_dc_irq()
1995 dc->stats.underflow++; in tegra_dc_irq()
2002 dc->stats.overflow++; in tegra_dc_irq()
2006 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
2007 dc->stats.underflow++; in tegra_dc_irq()
2013 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) in tegra_dc_has_window_groups() argument
2017 if (!dc->soc->wgrps) in tegra_dc_has_window_groups()
2020 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_has_window_groups()
2021 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_has_window_groups()
2023 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) in tegra_dc_has_window_groups()
2034 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
2045 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_init()
2054 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2057 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
2058 if (!dc->syncpt) in tegra_dc_init()
2059 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
2067 if (dc->soc->wgrps) in tegra_dc_init()
2068 primary = tegra_dc_add_shared_planes(drm, dc); in tegra_dc_init()
2070 primary = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
2077 if (dc->soc->supports_cursor) { in tegra_dc_init()
2078 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
2085 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); in tegra_dc_init()
2092 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2097 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2103 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2104 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2106 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
2108 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2112 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2113 dev_name(dc->dev), dc); in tegra_dc_init()
2115 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2136 host1x_syncpt_free(dc->syncpt); in tegra_dc_init()
2143 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
2146 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_exit()
2152 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2154 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
2156 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2161 host1x_syncpt_free(dc->syncpt); in tegra_dc_exit()
2168 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_suspend() local
2172 err = reset_control_assert(dc->rst); in tegra_dc_runtime_suspend()
2178 if (dc->soc->has_powergate) in tegra_dc_runtime_suspend()
2179 tegra_powergate_power_off(dc->powergate); in tegra_dc_runtime_suspend()
2181 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_suspend()
2189 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_resume() local
2199 if (dc->soc->has_powergate) { in tegra_dc_runtime_resume()
2200 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_runtime_resume()
2201 dc->rst); in tegra_dc_runtime_resume()
2207 err = clk_prepare_enable(dc->clk); in tegra_dc_runtime_resume()
2213 err = reset_control_deassert(dc->rst); in tegra_dc_runtime_resume()
2223 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_resume()
2334 .dc = 0,
2339 .dc = 1,
2344 .dc = 1,
2349 .dc = 2,
2354 .dc = 2,
2359 .dc = 2,
2382 .dc = 0,
2387 .dc = 1,
2392 .dc = 1,
2397 .dc = 2,
2402 .dc = 2,
2407 .dc = 2,
2455 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
2461 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
2463 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
2478 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
2487 dc->pipe = value; in tegra_dc_parse_dt()
2494 struct tegra_dc *dc = dev_get_drvdata(dev); in tegra_dc_match_by_pipe() local
2497 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
2500 static int tegra_dc_couple(struct tegra_dc *dc) in tegra_dc_couple() argument
2507 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
2511 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, in tegra_dc_couple()
2517 dc->client.parent = &parent->client; in tegra_dc_couple()
2519 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); in tegra_dc_couple()
2527 struct tegra_dc *dc; in tegra_dc_probe() local
2530 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
2531 if (!dc) in tegra_dc_probe()
2534 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
2536 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
2537 dc->dev = &pdev->dev; in tegra_dc_probe()
2539 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
2543 err = tegra_dc_couple(dc); in tegra_dc_probe()
2547 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
2548 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
2550 return PTR_ERR(dc->clk); in tegra_dc_probe()
2553 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
2554 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
2556 return PTR_ERR(dc->rst); in tegra_dc_probe()
2560 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
2566 err = reset_control_assert(dc->rst); in tegra_dc_probe()
2572 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
2574 if (dc->soc->has_powergate) { in tegra_dc_probe()
2575 if (dc->pipe == 0) in tegra_dc_probe()
2576 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
2578 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
2580 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
2583 dc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dc_probe()
2584 if (IS_ERR(dc->regs)) in tegra_dc_probe()
2585 return PTR_ERR(dc->regs); in tegra_dc_probe()
2587 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
2588 if (dc->irq < 0) in tegra_dc_probe()
2591 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
2598 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n", in tegra_dc_probe()
2603 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
2606 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
2607 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
2608 dc->client.dev = &pdev->dev; in tegra_dc_probe()
2610 err = host1x_client_register(&dc->client); in tegra_dc_probe()
2621 tegra_dc_rgb_remove(dc); in tegra_dc_probe()
2628 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
2631 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
2638 err = tegra_dc_rgb_remove(dc); in tegra_dc_remove()