42 	    ((uint32_t) pbox->x1 & 0x000007ff) |  in savage_emit_clip_rect_s3d()
43 	    (((uint32_t) pbox->y1 << 16) & 0x07ff0000);  in savage_emit_clip_rect_s3d()
45 	    (((uint32_t) pbox->x2 - 1) & 0x000007ff) |  in savage_emit_clip_rect_s3d()
46 	    ((((uint32_t) pbox->y2 - 1) << 16) & 0x07ff0000);  in savage_emit_clip_rect_s3d()
68 	    ((uint32_t) pbox->x1 & 0x000007ff) |  in savage_emit_clip_rect_s4()
69 	    (((uint32_t) pbox->y1 << 12) & 0x00fff000);  in savage_emit_clip_rect_s4()
71 	    (((uint32_t) pbox->x2 - 1) & 0x000007ff) |  in savage_emit_clip_rect_s4()
72 	    ((((uint32_t) pbox->y2 - 1) << 12) & 0x00fff000);  in savage_emit_clip_rect_s4()
120 	return 0;  in savage_verify_texaddr()
133 } while (0)
141 		DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",  in savage_verify_state_s3d()
158 			return savage_verify_texaddr(dev_priv, 0,  in savage_verify_state_s3d()
162 	return 0;  in savage_verify_state_s3d()
169 	int ret = 0;  in savage_verify_state_s4()
173 		DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",  in savage_verify_state_s4()
191 			ret |= savage_verify_texaddr(dev_priv, 0,  in savage_verify_state_s4()
210 	unsigned int count2 = 0;  in savage_dispatch_state()
216 		return 0;  in savage_dispatch_state()
220 		if (ret != 0)  in savage_dispatch_state()
233 				return 0;  in savage_dispatch_state()
237 		if (ret != 0)  in savage_dispatch_state()
251 				return 0;  in savage_dispatch_state()
266 		while (count > 0) {  in savage_dispatch_state()
277 		count2 = 0;  in savage_dispatch_state()
282 	return 0;  in savage_dispatch_state()
289 	unsigned char reorder = 0;  in savage_dispatch_dma_prim()
303 		return 0;  in savage_dispatch_dma_prim()
311 		if (n % 3 != 0) {  in savage_dispatch_dma_prim()
332 		if (skip != 0) {  in savage_dispatch_dma_prim()
333 			DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);  in savage_dispatch_dma_prim()
341 			DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);  in savage_dispatch_dma_prim()
351 		DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",  in savage_dispatch_dma_prim()
374 		for (i = 0; i < 63; ++i)  in savage_dispatch_dma_prim()
376 		dev_priv->waiting = 0;  in savage_dispatch_dma_prim()
380 	while (n != 0) {  in savage_dispatch_dma_prim()
423 	return 0;  in savage_dispatch_dma_prim()
431 	unsigned char reorder = 0;  in savage_dispatch_vb_prim()
441 		return 0;  in savage_dispatch_vb_prim()
449 		if (n % 3 != 0) {  in savage_dispatch_vb_prim()
471 			DRM_ERROR("invalid skip flags 0x%04x\n", skip);  in savage_dispatch_vb_prim()
477 			DRM_ERROR("invalid skip flags 0x%04x\n", skip);  in savage_dispatch_vb_prim()
494 		DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",  in savage_dispatch_vb_prim()
500 	while (n != 0) {  in savage_dispatch_vb_prim()
542 	return 0;  in savage_dispatch_vb_prim()
550 	unsigned char reorder = 0;  in savage_dispatch_dma_idx()
563 		return 0;  in savage_dispatch_dma_idx()
571 		if (n % 3 != 0) {  in savage_dispatch_dma_idx()
590 		if (skip != 0) {  in savage_dispatch_dma_idx()
591 			DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);  in savage_dispatch_dma_idx()
599 			DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);  in savage_dispatch_dma_idx()
626 		for (i = 0; i < 63; ++i)  in savage_dispatch_dma_idx()
628 		dev_priv->waiting = 0;  in savage_dispatch_dma_idx()
632 	while (n != 0) {  in savage_dispatch_dma_idx()
637 		for (i = 0; i < count; ++i) {  in savage_dispatch_dma_idx()
639 				DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",  in savage_dispatch_dma_idx()
662 			BCI_DRAW_INDICES_S3D(count, prim, idx[0]);  in savage_dispatch_dma_idx()
672 			for (i = 0; i + 1 < count; i += 2)  in savage_dispatch_dma_idx()
684 	return 0;  in savage_dispatch_dma_idx()
693 	unsigned char reorder = 0;  in savage_dispatch_vb_idx()
702 		return 0;  in savage_dispatch_vb_idx()
710 		if (n % 3 != 0) {  in savage_dispatch_vb_idx()
730 			DRM_ERROR("invalid skip flags 0x%04x\n", skip);  in savage_dispatch_vb_idx()
736 			DRM_ERROR("invalid skip flags 0x%04x\n", skip);  in savage_dispatch_vb_idx()
753 	while (n != 0) {  in savage_dispatch_vb_idx()
758 		for (i = 0; i < count; ++i) {  in savage_dispatch_vb_idx()
760 				DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",  in savage_dispatch_vb_idx()
775 			for (i = 0; i < count; ++i) {  in savage_dispatch_vb_idx()
785 			for (i = 0; i < count; ++i) {  in savage_dispatch_vb_idx()
799 	return 0;  in savage_dispatch_vb_idx()
813 	if (nbox == 0)  in savage_dispatch_clear()
814 		return 0;  in savage_dispatch_clear()
818 	BCI_CMD_SET_ROP(clear_cmd, 0xCC);  in savage_dispatch_clear()
820 	nbufs = ((flags & SAVAGE_FRONT) ? 1 : 0) +  in savage_dispatch_clear()
821 	    ((flags & SAVAGE_BACK) ? 1 : 0) + ((flags & SAVAGE_DEPTH) ? 1 : 0);  in savage_dispatch_clear()
822 	if (nbufs == 0)  in savage_dispatch_clear()
823 		return 0;  in savage_dispatch_clear()
825 	if (data->clear1.mask != 0xffffffff) {  in savage_dispatch_clear()
832 	for (i = 0; i < nbox; ++i) {  in savage_dispatch_clear()
863 	if (data->clear1.mask != 0xffffffff) {  in savage_dispatch_clear()
867 		DMA_WRITE(0xffffffff);  in savage_dispatch_clear()
871 	return 0;  in savage_dispatch_clear()
881 	if (nbox == 0)  in savage_dispatch_swap()
882 		return 0;  in savage_dispatch_swap()
886 	BCI_CMD_SET_ROP(swap_cmd, 0xCC);  in savage_dispatch_swap()
888 	for (i = 0; i < nbox; ++i) {  in savage_dispatch_swap()
900 	return 0;  in savage_dispatch_swap()
915 	for (i = 0; i < nbox; ++i) {  in savage_dispatch_draw()
959 			if (ret != 0)  in savage_dispatch_draw()
964 	return 0;  in savage_dispatch_draw()
978 	int ret = 0;  in savage_bci_cmdbuf()
987 			    ("vertex buffer index %u out of range (0-%u)\n",  in savage_bci_cmdbuf()
1047 	i = 0;  in savage_bci_cmdbuf()
1057 		j = 0;  in savage_bci_cmdbuf()
1085 				if (ret != 0)  in savage_bci_cmdbuf()
1128 			DRM_ERROR("invalid command 0x%x\n",  in savage_bci_cmdbuf()
1135 		if (ret != 0) {  in savage_bci_cmdbuf()
1146 		if (ret != 0) {  in savage_bci_cmdbuf()