drm/rockchip/rockchip-mipi-csi-tx.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #define DRIVER_NAME    "rockchip-mipi-csi"
12 #define m_CONFIG_DONE			BIT(0)
13 #define m_CONFIG_DONE_IMD		BIT(4)
14 #define m_CONFIG_DONE_MODE		BIT(8)
24 #define m_CSITX_EN			BIT(0)
25 #define m_CPHY_EN			BIT(1)
26 #define m_DPHY_EN			BIT(2)
28 #define m_IDI_48BIT_EN			BIT(9)
37 #define m_SOFT_RESET			BIT(0)
41 #define m_BYPASS_SELECT			BIT(0)
45 #define m_VSYNC_ENABLE			BIT(0)
46 #define m_HSYNC_ENABLE			BIT(1)
47 #define m_IDI_WHOLE_FRM_EN		BIT(4)
48 #define m_VOP_WHOLE_FRM_EN		BIT(5)
55 #define m_NON_CONTINUES_MODE_EN		BIT(0)
56 #define m_CONT_MODE_CLK_SET		BIT(4)
57 #define m_CONT_MODE_CLK_CLR		BIT(8)
69 #define m_VOP_PATH_EN			BIT(0)
70 #define m_VOP_DT_USERDEFINE_EN		BIT(1)
71 #define m_VOP_VC_USERDEFINE_EN		BIT(2)
72 #define m_VOP_WC_USERDEFINE_EN		BIT(3)
76 #define m_VOP_WC_USERDEFINE		GENMASK(31, 16)
84 #define v_VOP_WC_USERDEFINE(x)		(((x) & 0xffff) << 16)
87 #define m_VOP_LINE_PADDING_EN		BIT(4)
89 #define m_VOP_PKT_PADDING_EN		BIT(8)
90 #define m_VOP_WC_ACTIVE			GENMASK(31, 16)
94 #define v_VOP_WC_ACTIVE(x)		(((x) & 0xff) << 16)
97 #define m_BYPASS_PATH_EN		BIT(0)
98 #define m_BYPASS_DT_USERDEFINE_EN	BIT(1)
99 #define m_BYPASS_VC_USERDEFINE_EN	BIT(2)
100 #define m_BYPASS_WC_USERDEFINE_EN	BIT(3)
104 #define m_BYPASS_WC_USERDEFINE		GENMASK(31, 16)
112 #define v_BYPASS_WC_USERDEFINE(x)	(((x) & 0xff) << 16)
115 #define m_BYPASS_LINE_PADDING_EN	BIT(4)
117 #define m_BYPASS_PKT_PADDING_EN		BIT(8)
118 #define m_BYPASS_WC_ACTIVE		GENMASK(31, 16)
122 #define v_BYPASS_WC_ACTIVE(x)		(((x) & 0xff) << 16)
126 #define m_DPHY_PLL_LOCK			BIT(0)
127 #define m_STOPSTATE_CLK			BIT(1)
134 #define m_INTR_MASK			GENMASK(26, 16)
135 #define m_FRM_ST_RX			BIT(0 + 16)
136 #define m_FRM_END_RX			BIT(1 + 16)
137 #define m_LINE_END_TX			BIT(2 + 16)
138 #define m_FRM_ST_TX			BIT(3 + 16)
139 #define m_FRM_END_TX			BIT(4 + 16)
140 #define m_LINE_END_RX			BIT(5 + 16)
141 #define m_LINE_FLAG0			BIT(6 + 16)
142 #define m_LINE_FLAG1			BIT(7 + 16)
143 #define m_STOP_STATE			BIT(8 + 16)
144 #define m_PLL_LOCK			BIT(9 + 16)
145 #define m_CSITX_IDLE			BIT(10 + 16)
164 #define m_ERR_INTR_MASK			GENMASK(27, 16)
165 #define m_IDI_HDR_FIFO_OVERFLOW		BIT(0 + 16)
166 #define m_IDI_HDR_FIFO_UNDERFLOW	BIT(1 + 16)
167 #define m_IDI_PLD_FIFO_OVERFLOW		BIT(2 + 16)
168 #define m_IDI_PLD_FIFO_UNDERFLOW	BIT(3 + 16)
169 #define m_HDR_FIFO_OVERFLOW		BIT(4 + 16)
170 #define m_HDR_FIFO_UNDERFLOW		BIT(5 + 16)
171 #define m_PLD_FIFO_OVERFLOW		BIT(6 + 16)
172 #define m_PLD_FIFO_UNDERFLOW		BIT(7 + 16)
173 #define m_OUTBUFFER_OVERFLOW		BIT(8 + 16)
174 #define m_OUTBUFFER_UNDERFLOW		BIT(9 + 16)
175 #define m_TX_TXREADYHS_OVERFLOW		BIT(10 + 16)
176 #define m_TX_TXREADYHS_UNDERFLOW	BIT(11 + 16)
212 #define GRF_REG_FIELD(reg, lsb, msb)	((reg << 16) | (lsb << 8) | (msb))
248 	/* Non-SNPS PHY */