111 /* The table is based on 27MHz DPHY pll reference clock. */
319 	if (csi->dphy.phy)  in rockchip_mipi_dphy_power_on()
320 		phy_power_on(csi->dphy.phy);  in rockchip_mipi_dphy_power_on()
329 	if (csi->dphy.phy)  in rockchip_mipi_dphy_power_off()
330 		phy_power_off(csi->dphy.phy);  in rockchip_mipi_dphy_power_off()
337 	/* enable csi tx, dphy and config lane num */  in rockchip_mipi_csi_tx_en()
361 	/* disable csi tx, dphy and config lane num */  in rockchip_mipi_csi_host_power_off()
372 				    INPUT_DIVIDER(csi->dphy.input_div));  in rockchip_mipi_csi_phy_pll_init()
374 				    LOOP_DIV_LOW_SEL(csi->dphy.feedback_div) |  in rockchip_mipi_csi_phy_pll_init()
379 				    LOOP_DIV_HIGH_SEL(csi->dphy.feedback_div) |  in rockchip_mipi_csi_phy_pll_init()
498 			dev_err(csi->dev, "DPHY clock freq is out of range\n");  in rockchip_mipi_csi_calc_bandwidth()
515 	pllref = DIV_ROUND_UP(clk_get_rate(csi->dphy.ref_clk), USEC_PER_SEC);  in rockchip_mipi_csi_get_lane_bps()
531 	csi->dphy.input_div = n;  in rockchip_mipi_csi_get_lane_bps()
532 	csi->dphy.feedback_div = m;  in rockchip_mipi_csi_get_lane_bps()
546 	rate = clk_round_rate(csi->dphy.hs_clk, bw);  in rockchip_mipi_csi_set_hs_clk()
547 	ret = clk_set_rate(csi->dphy.hs_clk, rate);  in rockchip_mipi_csi_set_hs_clk()
680 	/* Configures DPHY Selete */  in rockchip_mipi_dphy_init()
683 	/* Configures DPHY to work as a Master */  in rockchip_mipi_dphy_init()
700 	if (!csi->dphy.phy) {  in rockchip_mipi_dphy_init()
701 		/* reset dphy */  in rockchip_mipi_dphy_init()
705 		/* init dphy */  in rockchip_mipi_dphy_init()
721 		/* enable dphy */  in rockchip_mipi_dphy_init()
758 	clk_disable_unprepare(csi->dphy.hs_clk);  in rockchip_mipi_csi_post_disable()
759 	clk_disable_unprepare(csi->dphy.ref_clk);  in rockchip_mipi_csi_post_disable()
785 	if (csi->dphy.phy)  in rockchip_mipi_csi_pre_init()
850 	clk_prepare_enable(csi->dphy.ref_clk);  in rockchip_mipi_csi_pre_enable()
851 	clk_prepare_enable(csi->dphy.hs_clk);  in rockchip_mipi_csi_pre_enable()
1206 	csi->dphy.phy = devm_phy_optional_get(dev, "mipi_dphy");  in rockchip_mipi_dphy_attach()
1207 	if (IS_ERR(csi->dphy.phy)) {  in rockchip_mipi_dphy_attach()
1208 		ret = PTR_ERR(csi->dphy.phy);  in rockchip_mipi_dphy_attach()
1209 		dev_err(dev, "failed to get mipi dphy: %d\n", ret);  in rockchip_mipi_dphy_attach()
1213 	if (csi->dphy.phy) {  in rockchip_mipi_dphy_attach()
1216 		csi->dphy.hs_clk = devm_clk_get(dev, "hs_clk");  in rockchip_mipi_dphy_attach()
1217 		if (IS_ERR(csi->dphy.hs_clk)) {  in rockchip_mipi_dphy_attach()
1219 			return PTR_ERR(csi->dphy.hs_clk);  in rockchip_mipi_dphy_attach()
1223 		csi->dphy.ref_clk = devm_clk_get(dev, "ref");  in rockchip_mipi_dphy_attach()
1224 		if (IS_ERR(csi->dphy.ref_clk)) {  in rockchip_mipi_dphy_attach()
1226 			return PTR_ERR(csi->dphy.ref_clk);  in rockchip_mipi_dphy_attach()