32 #define DSI_PHY_TMR_LPCLK_CFG		0x98
33 #define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) << 16)
34 #define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 0x3ff)
36 #define DSI_PHY_TMR_CFG			0x9c
37 #define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) << 24)
38 #define PHY_LP2HS_TIME(lbcc)		(((lbcc) & 0xff) << 16)
39 #define MAX_RD_TIME(lbcc)		((lbcc) & 0x7fff)
41 #define DSI_PHY_RSTZ			0xa0
42 #define PHY_DISFORCEPLL			0
44 #define PHY_DISABLECLK			0
46 #define PHY_RSTZ			0
48 #define PHY_SHUTDOWNZ			0
49 #define PHY_UNSHUTDOWNZ			BIT(0)
50 #define DSI_PHY_TST_CTRL0		0xb4
52 #define PHY_UNTESTCLK			0
53 #define PHY_TESTCLR			BIT(0)
54 #define PHY_UNTESTCLR			0
56 #define DSI_PHY_TST_CTRL1		0xb8
58 #define PHY_UNTESTEN			0
59 #define PHY_TESTDOUT(n)			(((n) & 0xff) << 8)
60 #define PHY_TESTDIN(n)			(((n) & 0xff) << 0)
62 #define VCO_RANGE_CON_SEL(val)	(((val) & 0x7) << 3)
63 #define VCO_IN_CAP_CON_DEFAULT	(0x0 << 1)
64 #define VCO_IN_CAP_CON_LOW	(0x1 << 1)
65 #define VCO_IN_CAP_CON_HIGH	(0x2 << 1)
66 #define REF_BIAS_CUR_SEL	BIT(0)
71 #define LPF_RESISTORS_20_KOHM	0
72 #define HSFREQRANGE_SEL(val)	(((val) & 0x3f) << 1)
74 #define INPUT_DIVIDER(val)	(((val) - 1) & 0x7f)
75 #define LOW_PROGRAM_EN		0
77 #define LOOP_DIV_LOW_SEL(val)	(((val) - 1) & 0x1f)
78 #define LOOP_DIV_HIGH_SEL(val)	((((val) - 1) >> 5) & 0x1f)
85 #define BANDGAP_ON		BIT(0)
88 #define	TER_RESISTOR_LOW	0
91 #define SETRD_MAX		(0x7 << 2)
93 #define TER_RESISTORS_ON	BIT(0)
95 #define BIASEXTR_SEL(val)	((val) & 0x7)
96 #define BANDGAP_SEL(val)	((val) & 0x7)
101 #define FPGA_DSI_PHY_TST_READ		0x18
102 #define FPGA_DSI_PHY_TST_CTRL0		0x20
113 	{  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
114 	{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
115 	{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
116 	{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
117 	{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
118 	{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
119 	{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
120 	{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
121 	{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
122 	{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
187 	reg = (field >> 16) & 0xffff;  in grf_field_write()
188 	lsb = (field >>  8) & 0xff;  in grf_field_write()
189 	msb = (field >>  0) & 0xff;  in grf_field_write()
223 	for (i = 0; i < ARRAY_SIZE(dp_tdin_map); i++)  in phy_max_mbps_to_testdin()
250 	 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content  in rockchip_mipi_csi_phy_write()
254 	writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_mipi_csi_phy_write()
255 	writel(0x00ff0000 | test_code,  in rockchip_mipi_csi_phy_write()
257 	writel(0x02000200, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_mipi_csi_phy_write()
258 	writel(0x01000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_mipi_csi_phy_write()
259 	writel(0x02000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_mipi_csi_phy_write()
260 	writel(0x01000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_mipi_csi_phy_write()
261 	writel(0x00ff0000 | test_data,  in rockchip_mipi_csi_phy_write()
263 	writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_mipi_csi_phy_write()
271 	writel(0x02ff0200 | test_code,  in rockchip_mipi_csi_phy_read()
273 	writel(0x01000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_mipi_csi_phy_read()
275 	val = readl(csi->test_code_regs + FPGA_DSI_PHY_TST_READ) & 0xff;  in rockchip_mipi_csi_phy_read()
276 	writel(0x03000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_mipi_csi_phy_read()
283 	writel(0x04000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_reset()
284 	writel(0x08000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_reset()
285 	writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_reset()
286 	writel(0x80008000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_reset()
287 	writel(0x80000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_reset()
288 	writel(0x40004000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_reset()
293 	writel(0x01000100, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_enable()
294 	writel(0x02000000, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_enable()
295 	writel(0x08000800, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_enable()
296 	writel(0x04000400, csi->test_code_regs + FPGA_DSI_PHY_TST_CTRL0);  in rockchip_bidir4l_board_phy_enable()
305 	writel(m_FRM_END_TX | v_FRM_END_TX(0), csi->regs + CSITX_INTR_EN);  in rockchip_mipi_csi_irq_init()
324 	return 0;  in rockchip_mipi_dphy_power_on()
351 	val = v_CONFIG_DONE(0) | v_CONFIG_DONE_IMD(1) | v_CONFIG_DONE_MODE(0);  in rockchip_mipi_csi_host_power_on()
363 	val = v_CSITX_EN(0) | v_DPHY_EN(0);  in rockchip_mipi_csi_host_power_off()
371 	rockchip_mipi_csi_phy_write(csi, 0x17,  in rockchip_mipi_csi_phy_pll_init()
373 	rockchip_mipi_csi_phy_write(csi, 0x18,  in rockchip_mipi_csi_phy_pll_init()
376 	rockchip_mipi_csi_phy_write(csi, 0x19,  in rockchip_mipi_csi_phy_pll_init()
378 	rockchip_mipi_csi_phy_write(csi, 0x18,  in rockchip_mipi_csi_phy_pll_init()
381 	rockchip_mipi_csi_phy_write(csi, 0x19,  in rockchip_mipi_csi_phy_pll_init()
390 	vco = (csi->lane_mbps < 200) ? 0 : (csi->lane_mbps + 100) / 200;  in rockchip_mipi_csi_phy_init()
393 	if (testdin < 0) {  in rockchip_mipi_csi_phy_init()
400 	rockchip_mipi_csi_phy_write(csi, 0xb0, 0x01);  in rockchip_mipi_csi_phy_init()
401 	rockchip_mipi_csi_phy_write(csi, 0xac, csi->lanes - 1);  in rockchip_mipi_csi_phy_init()
402 	rockchip_mipi_csi_phy_write(csi, 0xb1, 0x00);  in rockchip_mipi_csi_phy_init()
403 	rockchip_mipi_csi_phy_write(csi, 0xb2, 0x00);  in rockchip_mipi_csi_phy_init()
404 	rockchip_mipi_csi_phy_write(csi, 0xb3, 0x00);  in rockchip_mipi_csi_phy_init()
405 	rockchip_mipi_csi_phy_write(csi, 0x10, BYPASS_VCO_RANGE |  in rockchip_mipi_csi_phy_init()
410 	rockchip_mipi_csi_phy_write(csi, 0x11, CP_CURRENT_3MA);  in rockchip_mipi_csi_phy_init()
411 	rockchip_mipi_csi_phy_write(csi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |  in rockchip_mipi_csi_phy_init()
414 	rockchip_mipi_csi_phy_write(csi, 0x44, HSFREQRANGE_SEL(testdin));  in rockchip_mipi_csi_phy_init()
418 	rockchip_mipi_csi_phy_write(csi, 0x20, POWER_CONTROL |  in rockchip_mipi_csi_phy_init()
422 	rockchip_mipi_csi_phy_write(csi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |  in rockchip_mipi_csi_phy_init()
424 	rockchip_mipi_csi_phy_write(csi, 0x21, TER_RESISTOR_HIGH |  in rockchip_mipi_csi_phy_init()
428 	rockchip_mipi_csi_phy_write(csi, 0x22, LOW_PROGRAM_EN |  in rockchip_mipi_csi_phy_init()
430 	rockchip_mipi_csi_phy_write(csi, 0x22, HIGH_PROGRAM_EN |  in rockchip_mipi_csi_phy_init()
433 	rockchip_mipi_csi_phy_write(csi, 0x70, TLP_PROGRAM_EN | 0xf);  in rockchip_mipi_csi_phy_init()
434 	rockchip_mipi_csi_phy_write(csi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);  in rockchip_mipi_csi_phy_init()
435 	rockchip_mipi_csi_phy_write(csi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);  in rockchip_mipi_csi_phy_init()
437 	return 0;  in rockchip_mipi_csi_phy_init()
481 	if (bpp < 0) {  in rockchip_mipi_csi_calc_bandwidth()
526 		if (tmp == 0)  in rockchip_mipi_csi_get_lane_bps()
534 	return 0;  in rockchip_mipi_csi_get_lane_bps()
560 	if (device->lanes == 0 || device->lanes > 8) {  in rockchip_mipi_csi_host_attach()
571 	return 0;  in rockchip_mipi_csi_host_attach()
583 	return 0;  in rockchip_mipi_csi_host_detach()
594 	u32 vop_wc = 0;  in rockchip_mipi_csi_path_config()
595 	u32 data_type = 0x2a;  in rockchip_mipi_csi_path_config()
600 		data_type = 0x2a;  in rockchip_mipi_csi_path_config()
604 		data_type = 0x2b;  in rockchip_mipi_csi_path_config()
608 		data_type = 0x2a;  in rockchip_mipi_csi_path_config()
615 		val = v_BYPASS_SELECT(0);  in rockchip_mipi_csi_path_config()
632 		val = v_BYPASS_PATH_EN(0);  in rockchip_mipi_csi_path_config()
645 		val = v_VOP_PATH_EN(0) | v_VOP_WC_USERDEFINE_EN(0) |  in rockchip_mipi_csi_path_config()
646 			v_VOP_DT_USERDEFINE_EN(0);  in rockchip_mipi_csi_path_config()
656 		val = v_IDI_48BIT_EN(0);  in rockchip_mipi_csi_path_config()
667 		val = v_NON_CONTINUES_MODE_EN(1) | v_CONT_MODE_CLK_SET(0);  in rockchip_mipi_csi_video_mode_config()
670 		val = v_NON_CONTINUES_MODE_EN(0) | v_CONT_MODE_CLK_SET(1);  in rockchip_mipi_csi_video_mode_config()
678 	u32 map[] = {0x1, 0x3, 0x7, 0xf};  in rockchip_mipi_dphy_init()
681 	grf_field_write(csi, DPHY_SEL, 0);  in rockchip_mipi_dphy_init()
687 	grf_field_write(csi, BASEDIR, 0);  in rockchip_mipi_dphy_init()
690 	grf_field_write(csi, TURNREQUEST, 0);  in rockchip_mipi_dphy_init()
691 	grf_field_write(csi, TURNDISABLE, 0);  in rockchip_mipi_dphy_init()
692 	grf_field_write(csi, FORCETXSTOPMODE, 0);  in rockchip_mipi_dphy_init()
693 	grf_field_write(csi, FORCERXMODE, 0);  in rockchip_mipi_dphy_init()
706 		rockchip_mipi_csi_phy_write(csi, 0xb0, 0x01);  in rockchip_mipi_dphy_init()
707 		rockchip_mipi_csi_phy_write(csi, 0xac, csi->lanes - 1);  in rockchip_mipi_dphy_init()
709 		rockchip_mipi_csi_phy_write(csi, 0x44, 0x0a);/* fpga:324Mbps */  in rockchip_mipi_dphy_init()
710 		rockchip_mipi_csi_phy_write(csi, 0x19, 0x30);  in rockchip_mipi_dphy_init()
711 		rockchip_mipi_csi_phy_write(csi, 0x17, 0x00);  in rockchip_mipi_dphy_init()
712 		rockchip_mipi_csi_phy_write(csi, 0x18, 0xb);  in rockchip_mipi_dphy_init()
713 		rockchip_mipi_csi_phy_write(csi, 0x18, 0x80);  in rockchip_mipi_dphy_init()
715 		rockchip_mipi_csi_phy_write(csi, 0x10, 0x80);  in rockchip_mipi_dphy_init()
716 		rockchip_mipi_csi_phy_write(csi, 0x11, 0x09);  in rockchip_mipi_dphy_init()
717 		rockchip_mipi_csi_phy_write(csi, 0x12, 0xc2);  in rockchip_mipi_dphy_init()
797 	u32 map[] = {0x3, 0x7, 0xf, 0x1f};  in rockchip_mipi_csihost_enable_phy()
816 	int ret = 0;  in rockchip_mipi_csi_calibration()
820 	grf_field_write(csi, TXSKEWCALHS, 0x1f);  in rockchip_mipi_csi_calibration()
822 	grf_field_write(csi, TXSKEWCALHS, 0x0);  in rockchip_mipi_csi_calibration()
827 	if (ret < 0) {  in rockchip_mipi_csi_calibration()
836 	if (ret < 0) {  in rockchip_mipi_csi_calibration()
842 	return 0;  in rockchip_mipi_csi_calibration()
847 	int i = 0;  in rockchip_mipi_csi_pre_enable()
856 	for (i = 0; i < csi->pdata->rsts_num; i++) {  in rockchip_mipi_csi_pre_enable()
861 	for (i = 0; i < csi->pdata->rsts_num; i++) {  in rockchip_mipi_csi_pre_enable()
882 	return 0;  in rockchip_mipi_csi_pre_enable()
923 		s->bus_format = info->bus_formats[0];  in rockchip_mipi_csi_encoder_atomic_check()
930 	return 0;  in rockchip_mipi_csi_encoder_atomic_check()
981 	return 0;  in rockchip_mipi_loader_protect()
993 	val = v_CONFIG_DONE(0) | v_CONFIG_DONE_IMD(1) | v_CONFIG_DONE_MODE(0);  in rockchip_mipi_csi_connector_atomic_flush()
1031 		return 0;  in rockchip_mipi_csi_connector_set_property()
1048 		return 0;  in rockchip_mipi_csi_connector_get_property()
1072 	prop = drm_property_create_range(csi->connector.dev, 0,  in rockchip_mipi_csi_property_create()
1074 					 0, 0x1);  in rockchip_mipi_csi_property_create()
1077 		drm_object_attach_property(&csi->connector.base, prop, 0);  in rockchip_mipi_csi_property_create()
1080 	return 0;  in rockchip_mipi_csi_property_create()
1099 	if (encoder->possible_crtcs == 0)  in rockchip_mipi_csi_register()
1131 	return 0;  in rockchip_mipi_csi_register()
1185 	for (i = 0; i < ARRAY_SIZE(csi_tx_intr); i++)  in rockchip_mipi_csi_irq_handler()
1190 	for (i = 0; i < ARRAY_SIZE(csi_tx_err_intr); i++)  in rockchip_mipi_csi_irq_handler()
1230 	return 0;  in rockchip_mipi_dphy_attach()
1253 	return 0;  in dw_mipi_csi_parse_dt()
1293 	csi->irq = platform_get_irq(pdev, 0);  in rockchip_mipi_csi_probe()
1294 	if (csi->irq < 0) {  in rockchip_mipi_csi_probe()
1312 	for (i = 0; i < csi->pdata->rsts_num; i++) {  in rockchip_mipi_csi_probe()
1357 	return 0;  in rockchip_mipi_csi_remove()
1361 	[DPHY_SEL]		= GRF_REG_FIELD(0x0440,  8,  8),
1362 	[TXSKEWCALHS]		= GRF_REG_FIELD(0x0444, 11, 15),
1363 	[FORCETXSTOPMODE]	= GRF_REG_FIELD(0x0444,  7, 10),
1364 	[FORCERXMODE]		= GRF_REG_FIELD(0x0444,  6,  6),
1365 	[TURNDISABLE]		= GRF_REG_FIELD(0x0444,  5,  5),