Lines Matching full:hdmi
52 /* need to be unset if hdmi or i2c should control voltage */
146 * @ddc_en_reg: grf register offset of hdmi ddc enable
147 * @lcdsel_big: reg value of selecting vop big for HDMI
148 * @lcdsel_lit: reg value of selecting vop little for HDMI
186 struct dw_hdmi *hdmi; member
803 hdmi_get_tmdsclock(struct rockchip_hdmi *hdmi, unsigned long pixelclock) in hdmi_get_tmdsclock() argument
807 hdmi_bus_fmt_color_depth(hdmi->output_bus_format); in hdmi_get_tmdsclock()
809 if (!hdmi_bus_fmt_is_yuv422(hdmi->output_bus_format)) { in hdmi_get_tmdsclock()
830 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); in rockchip_hdmi_match_by_id() local
833 return hdmi->id == *id; in rockchip_hdmi_match_by_id()
848 static void hdmi_select_link_config(struct rockchip_hdmi *hdmi, in hdmi_select_link_config() argument
858 if (hdmi->plat_data->split_mode) in hdmi_select_link_config()
861 max_lanes = hdmi->max_lanes; in hdmi_select_link_config()
862 max_rate_per_lane = hdmi->max_frl_rate_per_lane; in hdmi_select_link_config()
865 hdmi->link_cfg.dsc_mode = false; in hdmi_select_link_config()
866 hdmi->link_cfg.frl_lanes = max_lanes; in hdmi_select_link_config()
867 hdmi->link_cfg.rate_per_lane = max_rate_per_lane; in hdmi_select_link_config()
868 hdmi->link_cfg.add_func = hdmi->add_func; in hdmi_select_link_config()
871 dev_info(hdmi->dev, "use tmds mode\n"); in hdmi_select_link_config()
872 hdmi->link_cfg.frl_mode = false; in hdmi_select_link_config()
876 hdmi->link_cfg.frl_mode = true; in hdmi_select_link_config()
878 if (!hdmi->dsc_cap.v_1p2) in hdmi_select_link_config()
881 max_dsc_lanes = hdmi->dsc_cap.max_lanes; in hdmi_select_link_config()
883 hdmi->dsc_cap.max_frl_rate_per_lane; in hdmi_select_link_config()
886 !hdmi_bus_fmt_is_yuv420(hdmi->bus_format) && in hdmi_select_link_config()
887 !hdmi_bus_fmt_is_yuv422(hdmi->bus_format)) { in hdmi_select_link_config()
888 hdmi->link_cfg.dsc_mode = true; in hdmi_select_link_config()
889 hdmi->link_cfg.frl_lanes = max_dsc_lanes; in hdmi_select_link_config()
890 hdmi->link_cfg.rate_per_lane = max_dsc_rate_per_lane; in hdmi_select_link_config()
892 hdmi->link_cfg.dsc_mode = false; in hdmi_select_link_config()
893 hdmi->link_cfg.frl_lanes = max_lanes; in hdmi_select_link_config()
894 hdmi->link_cfg.rate_per_lane = max_rate_per_lane; in hdmi_select_link_config()
918 static int hdmi_dsc_get_num_slices(struct rockchip_hdmi *hdmi, in hdmi_dsc_get_num_slices() argument
952 if (hdmi_bus_fmt_is_yuv444(hdmi->output_bus_format) || in hdmi_dsc_get_num_slices()
953 hdmi_bus_fmt_is_rgb(hdmi->output_bus_format)) in hdmi_dsc_get_num_slices()
988 * of PCON encoder and HDMI decoder can support. in hdmi_dsc_get_num_slices()
1014 static int hdmi_dsc_slices(struct rockchip_hdmi *hdmi, in hdmi_dsc_slices() argument
1017 int hdmi_throughput = hdmi->dsc_cap.clk_per_slice; in hdmi_dsc_slices()
1018 int hdmi_max_slices = hdmi->dsc_cap.max_slices; in hdmi_dsc_slices()
1022 return hdmi_dsc_get_num_slices(hdmi, crtc_state, rk_max_slices, in hdmi_dsc_slices()
1028 hdmi_dsc_get_bpp(struct rockchip_hdmi *hdmi, int src_fractional_bpp, in hdmi_dsc_get_bpp() argument
1044 * for each bpp we check if no of bytes can be supported by HDMI sink in hdmi_dsc_get_bpp()
1103 dw_hdmi_dsc_bpp(struct rockchip_hdmi *hdmi, in dw_hdmi_dsc_bpp() argument
1106 bool hdmi_all_bpp = hdmi->dsc_cap.all_bpp; in dw_hdmi_dsc_bpp()
1108 int hdmi_max_chunk_bytes = hdmi->dsc_cap.total_chunk_kbytes * 1024; in dw_hdmi_dsc_bpp()
1110 return hdmi_dsc_get_bpp(hdmi, fractional_bpp, slice_width, in dw_hdmi_dsc_bpp()
1115 static int dw_hdmi_qp_set_link_cfg(struct rockchip_hdmi *hdmi, in dw_hdmi_qp_set_link_cfg() argument
1129 hdmi_bus_fmt_is_rgb(hdmi->output_bus_format) == pps_datas[i].convert_rgb) in dw_hdmi_qp_set_link_cfg()
1133 dev_err(hdmi->dev, "can't find pps cfg!\n"); in dw_hdmi_qp_set_link_cfg()
1137 memcpy(hdmi->link_cfg.pps_payload, pps_datas[i].raw_pps, 128); in dw_hdmi_qp_set_link_cfg()
1138 hdmi->link_cfg.hcactive = DIV_ROUND_UP(slice_width * (bits_per_pixel / 16), 8) * in dw_hdmi_qp_set_link_cfg()
1144 static void dw_hdmi_qp_dsc_configure(struct rockchip_hdmi *hdmi, in dw_hdmi_qp_dsc_configure() argument
1154 unsigned int depth = hdmi_bus_fmt_color_depth(hdmi->output_bus_format); in dw_hdmi_qp_dsc_configure()
1159 hdmi_is_dsc_1_2 = hdmi->dsc_cap.v_1p2; in dw_hdmi_qp_dsc_configure()
1168 slice_count = hdmi_dsc_slices(hdmi, crtc_state); in dw_hdmi_qp_dsc_configure()
1174 bits_per_pixel = dw_hdmi_dsc_bpp(hdmi, slice_count, slice_width); in dw_hdmi_qp_dsc_configure()
1178 ret = dw_hdmi_qp_set_link_cfg(hdmi, crtc_state->mode.hdisplay, in dw_hdmi_qp_dsc_configure()
1183 dev_err(hdmi->dev, "set vdsc cfg failed\n"); in dw_hdmi_qp_dsc_configure()
1186 dev_info(hdmi->dev, "dsc_enable\n"); in dw_hdmi_qp_dsc_configure()
1196 memcpy(&s->pps, hdmi->link_cfg.pps_payload, 128); in dw_hdmi_qp_dsc_configure()
1200 static int rockchip_hdmi_update_phy_table(struct rockchip_hdmi *hdmi, in rockchip_hdmi_update_phy_table() argument
1207 dev_err(hdmi->dev, "phy table array number is out of range\n"); in rockchip_hdmi_update_phy_table()
1226 struct rockchip_hdmi *hdmi = container_of(p_work, struct rockchip_hdmi, work.work); in repo_hpd_event() local
1229 change = drm_helper_hpd_irq_event(hdmi->drm_dev); in repo_hpd_event()
1231 dev_dbg(hdmi->dev, "hpd stat changed:%d\n", hdmi->hpd_stat); in repo_hpd_event()
1232 dw_hdmi_qp_cec_set_hpd(hdmi->hdmi_qp, hdmi->hpd_stat, change); in repo_hpd_event()
1238 struct rockchip_hdmi *hdmi = dev_id; in rockchip_hdmi_hardirq() local
1241 regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); in rockchip_hdmi_hardirq()
1244 dev_dbg(hdmi->dev, "hpd irq %#x\n", intr_stat); in rockchip_hdmi_hardirq()
1246 if (!hdmi->id) in rockchip_hdmi_hardirq()
1252 regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); in rockchip_hdmi_hardirq()
1261 struct rockchip_hdmi *hdmi = dev_id; in rockchip_hdmi_irq() local
1266 regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); in rockchip_hdmi_irq()
1271 if (!hdmi->id) { in rockchip_hdmi_irq()
1287 regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); in rockchip_hdmi_irq()
1290 hdmi->hpd_stat = true; in rockchip_hdmi_irq()
1293 hdmi->hpd_stat = false; in rockchip_hdmi_irq()
1296 mod_delayed_work(hdmi->workqueue, &hdmi->work, msecs_to_jiffies(msecs)); in rockchip_hdmi_irq()
1298 if (!hdmi->id) { in rockchip_hdmi_irq()
1308 regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); in rockchip_hdmi_irq()
1313 static void init_hpd_work(struct rockchip_hdmi *hdmi) in init_hpd_work() argument
1315 hdmi->workqueue = create_workqueue("hpd_queue"); in init_hpd_work()
1316 INIT_DELAYED_WORK(&hdmi->work, repo_hpd_event); in init_hpd_work()
1322 struct rockchip_hdmi *hdmi = arg; in rockchip_hdmi_hpd_irq_handler() local
1324 val = gpiod_get_value(hdmi->hpd_gpiod); in rockchip_hdmi_hpd_irq_handler()
1327 if (hdmi->hdmi && hdmi->hpd_wake_en && hdmi->hpd_gpiod) in rockchip_hdmi_hpd_irq_handler()
1328 dw_hdmi_set_hpd_wake(hdmi->hdmi); in rockchip_hdmi_hpd_irq_handler()
1332 regmap_write(hdmi->regmap, RK3528_VO_GRF_HDMI_MASK, val); in rockchip_hdmi_hpd_irq_handler()
1337 static void dw_hdmi_rk3528_gpio_hpd_init(struct rockchip_hdmi *hdmi) in dw_hdmi_rk3528_gpio_hpd_init() argument
1341 if (hdmi->hpd_gpiod) { in dw_hdmi_rk3528_gpio_hpd_init()
1344 writel(val, hdmi->gpio_base + RK3528_GPIO_SWPORT_DR_L); in dw_hdmi_rk3528_gpio_hpd_init()
1355 regmap_write(hdmi->regmap, RK3528_VO_GRF_HDMI_MASK, val); in dw_hdmi_rk3528_gpio_hpd_init()
1357 val = gpiod_get_value(hdmi->hpd_gpiod); in dw_hdmi_rk3528_gpio_hpd_init()
1360 if (hdmi->hdmi && hdmi->hpd_wake_en && hdmi->hpd_gpiod) in dw_hdmi_rk3528_gpio_hpd_init()
1361 dw_hdmi_set_hpd_wake(hdmi->hdmi); in dw_hdmi_rk3528_gpio_hpd_init()
1365 regmap_write(hdmi->regmap, RK3528_VO_GRF_HDMI_MASK, val); in dw_hdmi_rk3528_gpio_hpd_init()
1368 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) in rockchip_hdmi_parse_dt() argument
1372 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
1374 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
1375 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
1376 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
1377 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
1380 if (hdmi->is_hdmi_qp) { in rockchip_hdmi_parse_dt()
1381 hdmi->vo1_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,vo1_grf"); in rockchip_hdmi_parse_dt()
1382 if (IS_ERR(hdmi->vo1_regmap)) { in rockchip_hdmi_parse_dt()
1383 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,vo1_grf\n"); in rockchip_hdmi_parse_dt()
1384 return PTR_ERR(hdmi->vo1_regmap); in rockchip_hdmi_parse_dt()
1388 hdmi->phyref_clk = devm_clk_get(hdmi->dev, "vpll"); in rockchip_hdmi_parse_dt()
1389 if (PTR_ERR(hdmi->phyref_clk) == -ENOENT) in rockchip_hdmi_parse_dt()
1390 hdmi->phyref_clk = devm_clk_get(hdmi->dev, "ref"); in rockchip_hdmi_parse_dt()
1392 if (PTR_ERR(hdmi->phyref_clk) == -ENOENT) { in rockchip_hdmi_parse_dt()
1393 hdmi->phyref_clk = NULL; in rockchip_hdmi_parse_dt()
1394 } else if (PTR_ERR(hdmi->phyref_clk) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
1396 } else if (IS_ERR(hdmi->phyref_clk)) { in rockchip_hdmi_parse_dt()
1397 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n"); in rockchip_hdmi_parse_dt()
1398 return PTR_ERR(hdmi->phyref_clk); in rockchip_hdmi_parse_dt()
1401 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf"); in rockchip_hdmi_parse_dt()
1402 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) { in rockchip_hdmi_parse_dt()
1403 hdmi->grf_clk = NULL; in rockchip_hdmi_parse_dt()
1404 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
1406 } else if (IS_ERR(hdmi->grf_clk)) { in rockchip_hdmi_parse_dt()
1407 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n"); in rockchip_hdmi_parse_dt()
1408 return PTR_ERR(hdmi->grf_clk); in rockchip_hdmi_parse_dt()
1411 hdmi->hclk_vio = devm_clk_get(hdmi->dev, "hclk_vio"); in rockchip_hdmi_parse_dt()
1412 if (PTR_ERR(hdmi->hclk_vio) == -ENOENT) { in rockchip_hdmi_parse_dt()
1413 hdmi->hclk_vio = NULL; in rockchip_hdmi_parse_dt()
1414 } else if (PTR_ERR(hdmi->hclk_vio) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
1416 } else if (IS_ERR(hdmi->hclk_vio)) { in rockchip_hdmi_parse_dt()
1417 dev_err(hdmi->dev, "failed to get hclk_vio clock\n"); in rockchip_hdmi_parse_dt()
1418 return PTR_ERR(hdmi->hclk_vio); in rockchip_hdmi_parse_dt()
1421 hdmi->hclk_vop = devm_clk_get(hdmi->dev, "hclk"); in rockchip_hdmi_parse_dt()
1422 if (PTR_ERR(hdmi->hclk_vop) == -ENOENT) { in rockchip_hdmi_parse_dt()
1423 hdmi->hclk_vop = NULL; in rockchip_hdmi_parse_dt()
1424 } else if (PTR_ERR(hdmi->hclk_vop) == -EPROBE_DEFER) { in rockchip_hdmi_parse_dt()
1426 } else if (IS_ERR(hdmi->hclk_vop)) { in rockchip_hdmi_parse_dt()
1427 dev_err(hdmi->dev, "failed to get hclk_vop clock\n"); in rockchip_hdmi_parse_dt()
1428 return PTR_ERR(hdmi->hclk_vop); in rockchip_hdmi_parse_dt()
1431 hdmi->aud_clk = devm_clk_get_optional(hdmi->dev, "aud"); in rockchip_hdmi_parse_dt()
1432 if (IS_ERR(hdmi->aud_clk)) { in rockchip_hdmi_parse_dt()
1433 dev_err_probe(hdmi->dev, PTR_ERR(hdmi->aud_clk), in rockchip_hdmi_parse_dt()
1435 return PTR_ERR(hdmi->aud_clk); in rockchip_hdmi_parse_dt()
1438 hdmi->hpd_clk = devm_clk_get_optional(hdmi->dev, "hpd"); in rockchip_hdmi_parse_dt()
1439 if (IS_ERR(hdmi->hpd_clk)) { in rockchip_hdmi_parse_dt()
1440 dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hpd_clk), in rockchip_hdmi_parse_dt()
1442 return PTR_ERR(hdmi->hpd_clk); in rockchip_hdmi_parse_dt()
1445 hdmi->hclk_vo1 = devm_clk_get_optional(hdmi->dev, "hclk_vo1"); in rockchip_hdmi_parse_dt()
1446 if (IS_ERR(hdmi->hclk_vo1)) { in rockchip_hdmi_parse_dt()
1447 dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hclk_vo1), in rockchip_hdmi_parse_dt()
1449 return PTR_ERR(hdmi->hclk_vo1); in rockchip_hdmi_parse_dt()
1452 hdmi->earc_clk = devm_clk_get_optional(hdmi->dev, "earc"); in rockchip_hdmi_parse_dt()
1453 if (IS_ERR(hdmi->earc_clk)) { in rockchip_hdmi_parse_dt()
1454 dev_err_probe(hdmi->dev, PTR_ERR(hdmi->earc_clk), in rockchip_hdmi_parse_dt()
1456 return PTR_ERR(hdmi->earc_clk); in rockchip_hdmi_parse_dt()
1459 hdmi->hdmitx_ref = devm_clk_get_optional(hdmi->dev, "hdmitx_ref"); in rockchip_hdmi_parse_dt()
1460 if (IS_ERR(hdmi->hdmitx_ref)) { in rockchip_hdmi_parse_dt()
1461 dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hdmitx_ref), in rockchip_hdmi_parse_dt()
1463 return PTR_ERR(hdmi->hdmitx_ref); in rockchip_hdmi_parse_dt()
1466 hdmi->pclk = devm_clk_get_optional(hdmi->dev, "pclk"); in rockchip_hdmi_parse_dt()
1467 if (IS_ERR(hdmi->pclk)) { in rockchip_hdmi_parse_dt()
1468 dev_err_probe(hdmi->dev, PTR_ERR(hdmi->pclk), in rockchip_hdmi_parse_dt()
1470 return PTR_ERR(hdmi->pclk); in rockchip_hdmi_parse_dt()
1473 hdmi->link_clk = devm_clk_get_optional(hdmi->dev, "link_clk"); in rockchip_hdmi_parse_dt()
1474 if (IS_ERR(hdmi->link_clk)) { in rockchip_hdmi_parse_dt()
1475 dev_err_probe(hdmi->dev, PTR_ERR(hdmi->link_clk), in rockchip_hdmi_parse_dt()
1477 return PTR_ERR(hdmi->link_clk); in rockchip_hdmi_parse_dt()
1480 hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable", in rockchip_hdmi_parse_dt()
1482 if (IS_ERR(hdmi->enable_gpio)) { in rockchip_hdmi_parse_dt()
1483 ret = PTR_ERR(hdmi->enable_gpio); in rockchip_hdmi_parse_dt()
1484 dev_err(hdmi->dev, "failed to request enable GPIO: %d\n", ret); in rockchip_hdmi_parse_dt()
1488 hdmi->skip_check_420_mode = in rockchip_hdmi_parse_dt()
1495 dev_err(hdmi->dev, "kmalloc phy table failed\n"); in rockchip_hdmi_parse_dt()
1502 ret = rockchip_hdmi_update_phy_table(hdmi, phy_config, in rockchip_hdmi_parse_dt()
1510 dev_dbg(hdmi->dev, "use default hdmi phy table\n"); in rockchip_hdmi_parse_dt()
1513 hdmi->hpd_gpiod = devm_gpiod_get_optional(hdmi->dev, "hpd", GPIOD_IN); in rockchip_hdmi_parse_dt()
1515 if (IS_ERR(hdmi->hpd_gpiod)) { in rockchip_hdmi_parse_dt()
1516 dev_err(hdmi->dev, "error getting HDP GPIO: %ld\n", in rockchip_hdmi_parse_dt()
1517 PTR_ERR(hdmi->hpd_gpiod)); in rockchip_hdmi_parse_dt()
1518 return PTR_ERR(hdmi->hpd_gpiod); in rockchip_hdmi_parse_dt()
1521 if (hdmi->hpd_gpiod) { in rockchip_hdmi_parse_dt()
1523 struct platform_device *pdev = to_platform_device(hdmi->dev); in rockchip_hdmi_parse_dt()
1526 hdmi->hpd_irq = gpiod_to_irq(hdmi->hpd_gpiod); in rockchip_hdmi_parse_dt()
1527 if (hdmi->hpd_irq < 0) in rockchip_hdmi_parse_dt()
1532 DRM_DEV_ERROR(hdmi->dev, "failed to get gpio regs\n"); in rockchip_hdmi_parse_dt()
1536 hdmi->gpio_base = devm_ioremap(hdmi->dev, res->start, resource_size(res)); in rockchip_hdmi_parse_dt()
1537 if (IS_ERR(hdmi->gpio_base)) { in rockchip_hdmi_parse_dt()
1538 DRM_DEV_ERROR(hdmi->dev, "Unable to get gpio ioregmap\n"); in rockchip_hdmi_parse_dt()
1539 return PTR_ERR(hdmi->gpio_base); in rockchip_hdmi_parse_dt()
1542 dw_hdmi_rk3528_gpio_hpd_init(hdmi); in rockchip_hdmi_parse_dt()
1543 ret = devm_request_threaded_irq(hdmi->dev, hdmi->hpd_irq, NULL, in rockchip_hdmi_parse_dt()
1548 "hdmi-hpd", hdmi); in rockchip_hdmi_parse_dt()
1550 dev_err(hdmi->dev, "failed to request hpd IRQ: %d\n", ret); in rockchip_hdmi_parse_dt()
1554 hdmi->hpd_wake_en = device_property_read_bool(hdmi->dev, "hpd-wake-up"); in rockchip_hdmi_parse_dt()
1555 if (hdmi->hpd_wake_en) in rockchip_hdmi_parse_dt()
1556 enable_irq_wake(hdmi->hpd_irq); in rockchip_hdmi_parse_dt()
1559 hdmi->p = devm_pinctrl_get(hdmi->dev); in rockchip_hdmi_parse_dt()
1560 if (IS_ERR(hdmi->p)) { in rockchip_hdmi_parse_dt()
1561 dev_err(hdmi->dev, "could not get pinctrl\n"); in rockchip_hdmi_parse_dt()
1562 return PTR_ERR(hdmi->p); in rockchip_hdmi_parse_dt()
1565 hdmi->idle_state = pinctrl_lookup_state(hdmi->p, "idle"); in rockchip_hdmi_parse_dt()
1566 if (IS_ERR(hdmi->idle_state)) { in rockchip_hdmi_parse_dt()
1567 dev_dbg(hdmi->dev, "idle state is not defined\n"); in rockchip_hdmi_parse_dt()
1571 hdmi->default_state = pinctrl_lookup_state(hdmi->p, "default"); in rockchip_hdmi_parse_dt()
1572 if (IS_ERR(hdmi->default_state)) { in rockchip_hdmi_parse_dt()
1573 dev_err(hdmi->dev, "could not find default state\n"); in rockchip_hdmi_parse_dt()
1574 return PTR_ERR(hdmi->default_state); in rockchip_hdmi_parse_dt()
1591 struct rockchip_hdmi *hdmi; in dw_hdmi_rockchip_mode_valid() local
1615 hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_mode_valid()
1622 if (!hdmi->skip_check_420_mode) { in dw_hdmi_rockchip_mode_valid()
1629 if (hdmi->max_tmdsclk <= 340000 && mode->clock > 340000 && in dw_hdmi_rockchip_mode_valid()
1634 if (hdmi->phy) { in dw_hdmi_rockchip_mode_valid()
1635 if (hdmi->is_hdmi_qp) in dw_hdmi_rockchip_mode_valid()
1636 phy_set_bus_width(hdmi->phy, mode->clock * 10); in dw_hdmi_rockchip_mode_valid()
1638 phy_set_bus_width(hdmi->phy, 8); in dw_hdmi_rockchip_mode_valid()
1667 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_encoder_disable() local
1675 if (hdmi->plat_data->split_mode) { in dw_hdmi_rockchip_encoder_disable()
1678 if (!hdmi->id) in dw_hdmi_rockchip_encoder_disable()
1685 * when plug out hdmi it will be switch cvbs and then phy bus width in dw_hdmi_rockchip_encoder_disable()
1688 if (hdmi->phy) in dw_hdmi_rockchip_encoder_disable()
1689 phy_set_bus_width(hdmi->phy, 8); in dw_hdmi_rockchip_encoder_disable()
1694 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_encoder_enable() local
1703 if (hdmi->phy) in dw_hdmi_rockchip_encoder_enable()
1704 phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); in dw_hdmi_rockchip_encoder_enable()
1706 clk_set_rate(hdmi->phyref_clk, in dw_hdmi_rockchip_encoder_enable()
1709 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_encoder_enable()
1710 if (hdmi->link_cfg.frl_mode) in dw_hdmi_rockchip_encoder_enable()
1711 gpiod_set_value(hdmi->enable_gpio, 0); in dw_hdmi_rockchip_encoder_enable()
1713 gpiod_set_value(hdmi->enable_gpio, 1); in dw_hdmi_rockchip_encoder_enable()
1716 if (hdmi->chip_data->lcdsel_grf_reg < 0) in dw_hdmi_rockchip_encoder_enable()
1719 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); in dw_hdmi_rockchip_encoder_enable()
1721 val = hdmi->chip_data->lcdsel_lit; in dw_hdmi_rockchip_encoder_enable()
1723 val = hdmi->chip_data->lcdsel_big; in dw_hdmi_rockchip_encoder_enable()
1725 ret = clk_prepare_enable(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
1727 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
1731 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val); in dw_hdmi_rockchip_encoder_enable()
1733 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
1735 if (hdmi->chip_data->lcdsel_grf_reg == RK3288_GRF_SOC_CON6) { in dw_hdmi_rockchip_encoder_enable()
1746 regmap_write(hdmi->regmap, RK3288_GRF_SOC_CON16, val); in dw_hdmi_rockchip_encoder_enable()
1749 clk_disable_unprepare(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
1750 DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n", in dw_hdmi_rockchip_encoder_enable()
1754 static int _dw_hdmi_rockchip_encoder_loader_protect(struct rockchip_hdmi *hdmi, bool on) in _dw_hdmi_rockchip_encoder_loader_protect() argument
1759 if (hdmi->is_hdmi_qp) { in _dw_hdmi_rockchip_encoder_loader_protect()
1760 ret = clk_prepare_enable(hdmi->link_clk); in _dw_hdmi_rockchip_encoder_loader_protect()
1762 DRM_DEV_ERROR(hdmi->dev, "failed to enable link_clk %d\n", ret); in _dw_hdmi_rockchip_encoder_loader_protect()
1767 hdmi->phy->power_count++; in _dw_hdmi_rockchip_encoder_loader_protect()
1769 clk_disable_unprepare(hdmi->link_clk); in _dw_hdmi_rockchip_encoder_loader_protect()
1770 hdmi->phy->power_count--; in _dw_hdmi_rockchip_encoder_loader_protect()
1778 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_encoder_loader_protect() local
1781 _dw_hdmi_rockchip_encoder_loader_protect(hdmi, on); in dw_hdmi_rockchip_encoder_loader_protect()
1782 if (hdmi->plat_data->right) { in dw_hdmi_rockchip_encoder_loader_protect()
1783 secondary = rockchip_hdmi_find_by_id(hdmi->dev->driver, !hdmi->id); in dw_hdmi_rockchip_encoder_loader_protect()
1790 static void rk3588_set_link_mode(struct rockchip_hdmi *hdmi) in rk3588_set_link_mode() argument
1795 if (!hdmi->id) in rk3588_set_link_mode()
1800 if (!hdmi->link_cfg.frl_mode) { in rk3588_set_link_mode()
1803 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON4, val); in rk3588_set_link_mode()
1805 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON7, val); in rk3588_set_link_mode()
1809 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); in rk3588_set_link_mode()
1811 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); in rk3588_set_link_mode()
1818 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON4, val); in rk3588_set_link_mode()
1820 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON7, val); in rk3588_set_link_mode()
1822 if (hdmi->link_cfg.dsc_mode) { in rk3588_set_link_mode()
1826 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); in rk3588_set_link_mode()
1828 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); in rk3588_set_link_mode()
1832 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); in rk3588_set_link_mode()
1834 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); in rk3588_set_link_mode()
1838 static void rk3588_set_color_format(struct rockchip_hdmi *hdmi, u64 bus_format, in rk3588_set_color_format() argument
1861 dev_err(hdmi->dev, "can't set correct color format\n"); in rk3588_set_color_format()
1865 if (hdmi->link_cfg.dsc_mode) in rk3588_set_color_format()
1873 if (!hdmi->id) in rk3588_set_color_format()
1874 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); in rk3588_set_color_format()
1876 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); in rk3588_set_color_format()
1881 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in rk3588_set_grf_cfg() local
1884 rk3588_set_link_mode(hdmi); in rk3588_set_grf_cfg()
1885 color_depth = hdmi_bus_fmt_color_depth(hdmi->bus_format); in rk3588_set_grf_cfg()
1886 rk3588_set_color_format(hdmi, hdmi->bus_format, color_depth); in rk3588_set_grf_cfg()
1891 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in rk3588_get_grf_color_fmt() local
1895 if (!hdmi->id) in rk3588_get_grf_color_fmt()
1896 regmap_read(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, &val); in rk3588_get_grf_color_fmt()
1898 regmap_read(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, &val); in rk3588_get_grf_color_fmt()
1925 dev_err(hdmi->dev, "can't get correct color format\n"); in rk3588_get_grf_color_fmt()
1936 struct rockchip_hdmi *hdmi, in dw_hdmi_rockchip_select_output() argument
1958 if (hdmi->plat_data->split_mode) { in dw_hdmi_rockchip_select_output()
1965 if (!hdmi->is_hdmi_qp) in dw_hdmi_rockchip_select_output()
1966 sink_is_hdmi = dw_hdmi_get_output_whether_hdmi(hdmi->hdmi); in dw_hdmi_rockchip_select_output()
1968 sink_is_hdmi = dw_hdmi_qp_get_output_whether_hdmi(hdmi->hdmi_qp); in dw_hdmi_rockchip_select_output()
1972 switch (hdmi->hdmi_output) { in dw_hdmi_rockchip_select_output()
1980 (pixclock >= 594000 && !hdmi->is_hdmi_qp)) in dw_hdmi_rockchip_select_output()
2020 info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) in dw_hdmi_rockchip_select_output()
2023 if (hdmi->colordepth > 8 && support_dc) in dw_hdmi_rockchip_select_output()
2043 hdmi->colorimetry = conn_state->colorspace; in dw_hdmi_rockchip_select_output()
2046 if ((hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_CYCC) && in dw_hdmi_rockchip_select_output()
2047 (hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_YCC) && in dw_hdmi_rockchip_select_output()
2048 hdmi->edid_colorimetry & (BIT(6) | BIT(7))) { in dw_hdmi_rockchip_select_output()
2052 } else if ((hdmi->colorimetry <= DRM_MODE_COLORIMETRY_BT2020_CYCC) && in dw_hdmi_rockchip_select_output()
2053 (hdmi->colorimetry >= DRM_MODE_COLORIMETRY_BT2020_YCC) && in dw_hdmi_rockchip_select_output()
2065 if ((yuv422_out || hdmi->hdmi_output == RK_IF_FORMAT_YCBCR_HQ) && color_depth == 10 && in dw_hdmi_rockchip_select_output()
2066 (hdmi_bus_fmt_color_depth(hdmi->prev_bus_format) == 8 || in dw_hdmi_rockchip_select_output()
2067 hdmi_bus_fmt_to_color_format(hdmi->prev_bus_format) == RK_IF_FORMAT_YCBCR422)) { in dw_hdmi_rockchip_select_output()
2079 if (hdmi->is_hdmi_qp && mode.clock >= 600000) in dw_hdmi_rockchip_select_output()
2094 max_tmds_clock = min(max_tmds_clock, hdmi->max_tmdsclk); in dw_hdmi_rockchip_select_output()
2096 if (hdmi->is_hdmi_qp && hdmi->link_cfg.rate_per_lane && mode.clock > 600000) in dw_hdmi_rockchip_select_output()
2098 hdmi->link_cfg.frl_lanes * hdmi->link_cfg.rate_per_lane * 1000000; in dw_hdmi_rockchip_select_output()
2124 !hdmi->unsupported_yuv_input) in dw_hdmi_rockchip_select_output()
2130 !hdmi->unsupported_yuv_input) in dw_hdmi_rockchip_select_output()
2141 hdmi->bus_format = *bus_format; in dw_hdmi_rockchip_select_output()
2144 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_select_output()
2146 hdmi->output_bus_format = MEDIA_BUS_FMT_YUYV12_1X24; in dw_hdmi_rockchip_select_output()
2148 hdmi->output_bus_format = MEDIA_BUS_FMT_YUYV10_1X20; in dw_hdmi_rockchip_select_output()
2150 hdmi->output_bus_format = MEDIA_BUS_FMT_YUYV8_1X16; in dw_hdmi_rockchip_select_output()
2152 *bus_format = hdmi->output_bus_format; in dw_hdmi_rockchip_select_output()
2153 hdmi->bus_format = *bus_format; in dw_hdmi_rockchip_select_output()
2157 hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY12_1X24; in dw_hdmi_rockchip_select_output()
2159 hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY10_1X20; in dw_hdmi_rockchip_select_output()
2161 hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY8_1X16; in dw_hdmi_rockchip_select_output()
2164 hdmi->output_bus_format = *bus_format; in dw_hdmi_rockchip_select_output()
2170 struct rockchip_hdmi *hdmi) in dw_hdmi_rockchip_check_color() argument
2175 unsigned long output_bus_format = hdmi->output_bus_format; in dw_hdmi_rockchip_check_color()
2176 unsigned long enc_out_encoding = hdmi->enc_out_encoding; in dw_hdmi_rockchip_check_color()
2180 dw_hdmi_rockchip_select_output(conn_state, crtc_state, hdmi, in dw_hdmi_rockchip_check_color()
2183 &hdmi->enc_out_encoding, &eotf); in dw_hdmi_rockchip_check_color()
2185 if (output_bus_format != hdmi->output_bus_format || in dw_hdmi_rockchip_check_color()
2186 enc_out_encoding != hdmi->enc_out_encoding) in dw_hdmi_rockchip_check_color()
2198 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_encoder_atomic_check() local
2207 * There are two hdmi but only one encoder in split mode, in dw_hdmi_rockchip_encoder_atomic_check()
2213 if (hdmi->plat_data->split_mode) in dw_hdmi_rockchip_encoder_atomic_check()
2216 dw_hdmi_rockchip_select_output(conn_state, crtc_state, hdmi, in dw_hdmi_rockchip_encoder_atomic_check()
2219 &hdmi->enc_out_encoding, &s->eotf); in dw_hdmi_rockchip_encoder_atomic_check()
2222 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_encoder_atomic_check()
2224 tmdsclk = hdmi_get_tmdsclock(hdmi, crtc_state->mode.clock); in dw_hdmi_rockchip_encoder_atomic_check()
2225 if (hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format)) in dw_hdmi_rockchip_encoder_atomic_check()
2227 hdmi_select_link_config(hdmi, crtc_state, tmdsclk); in dw_hdmi_rockchip_encoder_atomic_check()
2229 if (hdmi->link_cfg.frl_mode) { in dw_hdmi_rockchip_encoder_atomic_check()
2231 if (hdmi->link_cfg.rate_per_lane >= 10) { in dw_hdmi_rockchip_encoder_atomic_check()
2232 hdmi->link_cfg.frl_lanes = 4; in dw_hdmi_rockchip_encoder_atomic_check()
2233 hdmi->link_cfg.rate_per_lane = 10; in dw_hdmi_rockchip_encoder_atomic_check()
2235 bus_width = hdmi->link_cfg.frl_lanes * in dw_hdmi_rockchip_encoder_atomic_check()
2236 hdmi->link_cfg.rate_per_lane * 1000000; in dw_hdmi_rockchip_encoder_atomic_check()
2244 bus_width = hdmi_get_tmdsclock(hdmi, mode.clock * 10); in dw_hdmi_rockchip_encoder_atomic_check()
2245 if (hdmi_bus_fmt_is_yuv420(hdmi->output_bus_format)) in dw_hdmi_rockchip_encoder_atomic_check()
2248 if (color_depth == 10 && !hdmi_bus_fmt_is_yuv422(hdmi->output_bus_format)) in dw_hdmi_rockchip_encoder_atomic_check()
2253 hdmi->phy_bus_width = bus_width; in dw_hdmi_rockchip_encoder_atomic_check()
2255 if (hdmi->phy) in dw_hdmi_rockchip_encoder_atomic_check()
2256 phy_set_bus_width(hdmi->phy, bus_width); in dw_hdmi_rockchip_encoder_atomic_check()
2261 if (hdmi->plat_data->split_mode) { in dw_hdmi_rockchip_encoder_atomic_check()
2263 if (hdmi->plat_data->right && hdmi->id) in dw_hdmi_rockchip_encoder_atomic_check()
2267 if (!hdmi->id) in dw_hdmi_rockchip_encoder_atomic_check()
2274 hdmi->bus_format = s->bus_format; in dw_hdmi_rockchip_encoder_atomic_check()
2276 if (hdmi->enc_out_encoding == V4L2_YCBCR_ENC_BT2020) in dw_hdmi_rockchip_encoder_atomic_check()
2280 else if (hdmi->enc_out_encoding == V4L2_YCBCR_ENC_709) in dw_hdmi_rockchip_encoder_atomic_check()
2285 if (hdmi->plat_data->split_mode && !secondary) { in dw_hdmi_rockchip_encoder_atomic_check()
2286 hdmi = rockchip_hdmi_find_by_id(hdmi->dev->driver, !hdmi->id); in dw_hdmi_rockchip_encoder_atomic_check()
2298 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_input_bus_format() local
2300 return hdmi->bus_format; in dw_hdmi_rockchip_get_input_bus_format()
2306 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_output_bus_format() local
2308 return hdmi->output_bus_format; in dw_hdmi_rockchip_get_output_bus_format()
2314 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_enc_in_encoding() local
2316 return hdmi->enc_out_encoding; in dw_hdmi_rockchip_get_enc_in_encoding()
2322 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_enc_out_encoding() local
2324 return hdmi->enc_out_encoding; in dw_hdmi_rockchip_get_enc_out_encoding()
2330 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_quant_range() local
2332 return hdmi->hdmi_quant_range; in dw_hdmi_rockchip_get_quant_range()
2338 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_hdr_property() local
2340 return hdmi->hdr_panel_metadata_property; in dw_hdmi_rockchip_get_hdr_property()
2346 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_hdr_blob() local
2348 return hdmi->hdr_panel_blob_ptr; in dw_hdmi_rockchip_get_hdr_blob()
2354 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_update_color_format() local
2356 dw_hdmi_rockchip_check_color(conn_state, hdmi); in dw_hdmi_rockchip_update_color_format()
2362 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_color_changed() local
2365 if (hdmi->color_changed) in dw_hdmi_rockchip_get_color_changed()
2367 hdmi->color_changed = 0; in dw_hdmi_rockchip_get_color_changed()
2385 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_edid_dsc_info() local
2390 memset(&hdmi->dsc_cap, 0, sizeof(hdmi->dsc_cap)); in dw_hdmi_rockchip_get_edid_dsc_info()
2391 hdmi->max_frl_rate_per_lane = 0; in dw_hdmi_rockchip_get_edid_dsc_info()
2392 hdmi->max_lanes = 0; in dw_hdmi_rockchip_get_edid_dsc_info()
2393 hdmi->add_func = 0; in dw_hdmi_rockchip_get_edid_dsc_info()
2395 return rockchip_drm_parse_cea_ext(&hdmi->dsc_cap, in dw_hdmi_rockchip_get_edid_dsc_info()
2396 &hdmi->max_frl_rate_per_lane, in dw_hdmi_rockchip_get_edid_dsc_info()
2397 &hdmi->max_lanes, &hdmi->add_func, edid); in dw_hdmi_rockchip_get_edid_dsc_info()
2405 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_next_hdr_data() local
2406 struct next_hdr_sink_data *sink_data = &hdmi->next_hdr_data; in dw_hdmi_rockchip_get_next_hdr_data()
2408 struct drm_property *property = hdmi->next_hdr_sink_data_property; in dw_hdmi_rockchip_get_next_hdr_data()
2409 struct drm_property_blob *blob = hdmi->hdr_panel_blob_ptr; in dw_hdmi_rockchip_get_next_hdr_data()
2424 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_colorimetry() local
2426 return rockchip_drm_parse_colorimetry_data_block(&hdmi->edid_colorimetry, edid); in dw_hdmi_rockchip_get_colorimetry()
2432 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_link_cfg() local
2434 return &hdmi->link_cfg; in dw_hdmi_rockchip_get_link_cfg()
2448 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_dclk_set() local
2455 dclk = devm_clk_get_optional(hdmi->dev, clk_name); in dw_hdmi_dclk_set()
2457 DRM_DEV_ERROR(hdmi->dev, "failed to get %s\n", clk_name); in dw_hdmi_dclk_set()
2460 if (hdmi->is_hdmi_qp) { in dw_hdmi_dclk_set()
2461 DRM_DEV_ERROR(hdmi->dev, "failed to get %s\n", clk_name); in dw_hdmi_dclk_set()
2471 DRM_DEV_ERROR(hdmi->dev, "failed to enable dclk for video port%d - %d\n", in dw_hdmi_dclk_set()
2482 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_link_clk_set() local
2483 u64 phy_clk = hdmi->phy_bus_width; in dw_hdmi_link_clk_set()
2487 ret = clk_prepare_enable(hdmi->link_clk); in dw_hdmi_link_clk_set()
2489 DRM_DEV_ERROR(hdmi->dev, "failed to enable link_clk %d\n", ret); in dw_hdmi_link_clk_set()
2500 * To be compatible with vop dclk usage scenarios, hdmi phy pll clk in dw_hdmi_link_clk_set()
2506 clk_get_rate(hdmi->link_clk); in dw_hdmi_link_clk_set()
2507 clk_set_rate(hdmi->link_clk, phy_clk); in dw_hdmi_link_clk_set()
2509 clk_disable_unprepare(hdmi->link_clk); in dw_hdmi_link_clk_set()
2518 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_check_hdr_color_change() local
2523 if (dw_hdmi_rockchip_check_color(conn_state, hdmi)) in dw_hdmi_rockchip_check_hdr_color_change()
2531 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_set_prev_bus_format() local
2533 hdmi->prev_bus_format = bus_format; in dw_hdmi_rockchip_set_prev_bus_format()
2538 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_set_ddc_io() local
2540 if (!hdmi->p || !hdmi->idle_state || !hdmi->default_state) in dw_hdmi_rockchip_set_ddc_io()
2544 if (pinctrl_select_state(hdmi->p, hdmi->idle_state)) in dw_hdmi_rockchip_set_ddc_io()
2545 dev_err(hdmi->dev, "could not select idle state\n"); in dw_hdmi_rockchip_set_ddc_io()
2547 if (pinctrl_select_state(hdmi->p, hdmi->default_state)) in dw_hdmi_rockchip_set_ddc_io()
2548 dev_err(hdmi->dev, "could not select default state\n"); in dw_hdmi_rockchip_set_ddc_io()
2582 { 1, "HDMI" },
2595 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_attach_properties() local
2601 hdmi->hdmi_output = RK_IF_FORMAT_RGB; in dw_hdmi_rockchip_attach_properties()
2602 hdmi->colordepth = 10; in dw_hdmi_rockchip_attach_properties()
2605 hdmi->hdmi_output = RK_IF_FORMAT_YCBCR444; in dw_hdmi_rockchip_attach_properties()
2606 hdmi->colordepth = 8; in dw_hdmi_rockchip_attach_properties()
2609 hdmi->hdmi_output = RK_IF_FORMAT_YCBCR444; in dw_hdmi_rockchip_attach_properties()
2610 hdmi->colordepth = 10; in dw_hdmi_rockchip_attach_properties()
2614 hdmi->hdmi_output = RK_IF_FORMAT_YCBCR422; in dw_hdmi_rockchip_attach_properties()
2615 hdmi->colordepth = 10; in dw_hdmi_rockchip_attach_properties()
2619 hdmi->hdmi_output = RK_IF_FORMAT_YCBCR422; in dw_hdmi_rockchip_attach_properties()
2620 hdmi->colordepth = 8; in dw_hdmi_rockchip_attach_properties()
2623 hdmi->hdmi_output = RK_IF_FORMAT_YCBCR420; in dw_hdmi_rockchip_attach_properties()
2624 hdmi->colordepth = 8; in dw_hdmi_rockchip_attach_properties()
2627 hdmi->hdmi_output = RK_IF_FORMAT_YCBCR420; in dw_hdmi_rockchip_attach_properties()
2628 hdmi->colordepth = 10; in dw_hdmi_rockchip_attach_properties()
2631 hdmi->hdmi_output = RK_IF_FORMAT_RGB; in dw_hdmi_rockchip_attach_properties()
2632 hdmi->colordepth = 8; in dw_hdmi_rockchip_attach_properties()
2635 hdmi->bus_format = color; in dw_hdmi_rockchip_attach_properties()
2636 hdmi->prev_bus_format = color; in dw_hdmi_rockchip_attach_properties()
2638 if (hdmi->hdmi_output == RK_IF_FORMAT_YCBCR422) { in dw_hdmi_rockchip_attach_properties()
2639 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_attach_properties()
2640 if (hdmi->colordepth == 12) in dw_hdmi_rockchip_attach_properties()
2641 hdmi->output_bus_format = MEDIA_BUS_FMT_YUYV12_1X24; in dw_hdmi_rockchip_attach_properties()
2642 else if (hdmi->colordepth == 10) in dw_hdmi_rockchip_attach_properties()
2643 hdmi->output_bus_format = MEDIA_BUS_FMT_YUYV10_1X20; in dw_hdmi_rockchip_attach_properties()
2645 hdmi->output_bus_format = MEDIA_BUS_FMT_YUYV8_1X16; in dw_hdmi_rockchip_attach_properties()
2647 if (hdmi->colordepth == 12) in dw_hdmi_rockchip_attach_properties()
2648 hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY12_1X24; in dw_hdmi_rockchip_attach_properties()
2649 else if (hdmi->colordepth == 10) in dw_hdmi_rockchip_attach_properties()
2650 hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY10_1X20; in dw_hdmi_rockchip_attach_properties()
2652 hdmi->output_bus_format = MEDIA_BUS_FMT_UYVY8_1X16; in dw_hdmi_rockchip_attach_properties()
2655 hdmi->output_bus_format = hdmi->bus_format; in dw_hdmi_rockchip_attach_properties()
2659 if (!hdmi->color_depth_property && !hdmi->unsupported_deep_color) { in dw_hdmi_rockchip_attach_properties()
2665 hdmi->color_depth_property = prop; in dw_hdmi_rockchip_attach_properties()
2674 hdmi->hdmi_output_property = prop; in dw_hdmi_rockchip_attach_properties()
2682 hdmi->colordepth_capacity = prop; in dw_hdmi_rockchip_attach_properties()
2690 hdmi->outputmode_capacity = prop; in dw_hdmi_rockchip_attach_properties()
2699 hdmi->hdr_panel_metadata_property = prop; in dw_hdmi_rockchip_attach_properties()
2708 hdmi->next_hdr_sink_data_property = prop; in dw_hdmi_rockchip_attach_properties()
2714 hdmi->allm_capacity = prop; in dw_hdmi_rockchip_attach_properties()
2716 !!(hdmi->add_func & SUPPORT_HDMI_ALLM)); in dw_hdmi_rockchip_attach_properties()
2724 hdmi->allm_enable = prop; in dw_hdmi_rockchip_attach_properties()
2727 hdmi->enable_allm = allm_en; in dw_hdmi_rockchip_attach_properties()
2734 hdmi->output_hdmi_dvi = prop; in dw_hdmi_rockchip_attach_properties()
2743 hdmi->output_type_capacity = prop; in dw_hdmi_rockchip_attach_properties()
2747 if (!hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_attach_properties()
2753 hdmi->quant_range = prop; in dw_hdmi_rockchip_attach_properties()
2759 if (hdmi->is_hdmi_qp) in dw_hdmi_rockchip_attach_properties()
2765 drm_object_attach_property(&connector->base, private->connector_id_prop, hdmi->id); in dw_hdmi_rockchip_attach_properties()
2772 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_destroy_properties() local
2774 if (hdmi->color_depth_property) { in dw_hdmi_rockchip_destroy_properties()
2776 hdmi->color_depth_property); in dw_hdmi_rockchip_destroy_properties()
2777 hdmi->color_depth_property = NULL; in dw_hdmi_rockchip_destroy_properties()
2780 if (hdmi->hdmi_output_property) { in dw_hdmi_rockchip_destroy_properties()
2782 hdmi->hdmi_output_property); in dw_hdmi_rockchip_destroy_properties()
2783 hdmi->hdmi_output_property = NULL; in dw_hdmi_rockchip_destroy_properties()
2786 if (hdmi->colordepth_capacity) { in dw_hdmi_rockchip_destroy_properties()
2788 hdmi->colordepth_capacity); in dw_hdmi_rockchip_destroy_properties()
2789 hdmi->colordepth_capacity = NULL; in dw_hdmi_rockchip_destroy_properties()
2792 if (hdmi->outputmode_capacity) { in dw_hdmi_rockchip_destroy_properties()
2794 hdmi->outputmode_capacity); in dw_hdmi_rockchip_destroy_properties()
2795 hdmi->outputmode_capacity = NULL; in dw_hdmi_rockchip_destroy_properties()
2798 if (hdmi->quant_range) { in dw_hdmi_rockchip_destroy_properties()
2800 hdmi->quant_range); in dw_hdmi_rockchip_destroy_properties()
2801 hdmi->quant_range = NULL; in dw_hdmi_rockchip_destroy_properties()
2804 if (hdmi->hdr_panel_metadata_property) { in dw_hdmi_rockchip_destroy_properties()
2806 hdmi->hdr_panel_metadata_property); in dw_hdmi_rockchip_destroy_properties()
2807 hdmi->hdr_panel_metadata_property = NULL; in dw_hdmi_rockchip_destroy_properties()
2810 if (hdmi->next_hdr_sink_data_property) { in dw_hdmi_rockchip_destroy_properties()
2812 hdmi->next_hdr_sink_data_property); in dw_hdmi_rockchip_destroy_properties()
2813 hdmi->next_hdr_sink_data_property = NULL; in dw_hdmi_rockchip_destroy_properties()
2816 if (hdmi->output_hdmi_dvi) { in dw_hdmi_rockchip_destroy_properties()
2818 hdmi->output_hdmi_dvi); in dw_hdmi_rockchip_destroy_properties()
2819 hdmi->output_hdmi_dvi = NULL; in dw_hdmi_rockchip_destroy_properties()
2822 if (hdmi->output_type_capacity) { in dw_hdmi_rockchip_destroy_properties()
2824 hdmi->output_type_capacity); in dw_hdmi_rockchip_destroy_properties()
2825 hdmi->output_type_capacity = NULL; in dw_hdmi_rockchip_destroy_properties()
2828 if (hdmi->allm_capacity) { in dw_hdmi_rockchip_destroy_properties()
2830 hdmi->allm_capacity); in dw_hdmi_rockchip_destroy_properties()
2831 hdmi->allm_capacity = NULL; in dw_hdmi_rockchip_destroy_properties()
2834 if (hdmi->allm_enable) { in dw_hdmi_rockchip_destroy_properties()
2835 drm_property_destroy(connector->dev, hdmi->allm_enable); in dw_hdmi_rockchip_destroy_properties()
2836 hdmi->allm_enable = NULL; in dw_hdmi_rockchip_destroy_properties()
2847 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_set_property() local
2850 if (property == hdmi->color_depth_property) { in dw_hdmi_rockchip_set_property()
2851 hdmi->colordepth = val; in dw_hdmi_rockchip_set_property()
2852 /* If hdmi is disconnected, state->crtc is null */ in dw_hdmi_rockchip_set_property()
2855 if (dw_hdmi_rockchip_check_color(state, hdmi)) in dw_hdmi_rockchip_set_property()
2856 hdmi->color_changed++; in dw_hdmi_rockchip_set_property()
2858 } else if (property == hdmi->hdmi_output_property) { in dw_hdmi_rockchip_set_property()
2859 hdmi->hdmi_output = val; in dw_hdmi_rockchip_set_property()
2862 if (dw_hdmi_rockchip_check_color(state, hdmi)) in dw_hdmi_rockchip_set_property()
2863 hdmi->color_changed++; in dw_hdmi_rockchip_set_property()
2865 } else if (property == hdmi->quant_range) { in dw_hdmi_rockchip_set_property()
2866 u64 quant_range = hdmi->hdmi_quant_range; in dw_hdmi_rockchip_set_property()
2868 hdmi->hdmi_quant_range = val; in dw_hdmi_rockchip_set_property()
2869 if (quant_range != hdmi->hdmi_quant_range) in dw_hdmi_rockchip_set_property()
2870 dw_hdmi_set_quant_range(hdmi->hdmi); in dw_hdmi_rockchip_set_property()
2874 } else if (property == hdmi->output_hdmi_dvi) { in dw_hdmi_rockchip_set_property()
2875 if (!hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_set_property()
2876 if (hdmi->force_output != val) in dw_hdmi_rockchip_set_property()
2877 hdmi->color_changed++; in dw_hdmi_rockchip_set_property()
2878 hdmi->force_output = val; in dw_hdmi_rockchip_set_property()
2879 dw_hdmi_set_output_type(hdmi->hdmi, val); in dw_hdmi_rockchip_set_property()
2881 hdmi->force_output = val; in dw_hdmi_rockchip_set_property()
2882 dw_hdmi_qp_set_output_type(hdmi->hdmi_qp, val); in dw_hdmi_rockchip_set_property()
2885 } else if (property == hdmi->colordepth_capacity) { in dw_hdmi_rockchip_set_property()
2887 } else if (property == hdmi->outputmode_capacity) { in dw_hdmi_rockchip_set_property()
2889 } else if (property == hdmi->output_type_capacity) { in dw_hdmi_rockchip_set_property()
2891 } else if (property == hdmi->allm_capacity) { in dw_hdmi_rockchip_set_property()
2893 } else if (property == hdmi->allm_enable) { in dw_hdmi_rockchip_set_property()
2894 u64 allm_enable = hdmi->enable_allm; in dw_hdmi_rockchip_set_property()
2896 hdmi->enable_allm = val; in dw_hdmi_rockchip_set_property()
2897 if (allm_enable != hdmi->enable_allm) in dw_hdmi_rockchip_set_property()
2898 dw_hdmi_qp_set_allm_enable(hdmi->hdmi_qp, hdmi->enable_allm); in dw_hdmi_rockchip_set_property()
2915 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_get_property() local
2919 if (property == hdmi->color_depth_property) { in dw_hdmi_rockchip_get_property()
2920 *val = hdmi->colordepth; in dw_hdmi_rockchip_get_property()
2922 } else if (property == hdmi->hdmi_output_property) { in dw_hdmi_rockchip_get_property()
2923 *val = hdmi->hdmi_output; in dw_hdmi_rockchip_get_property()
2925 } else if (property == hdmi->colordepth_capacity) { in dw_hdmi_rockchip_get_property()
2928 if (hdmi->unsupported_deep_color) in dw_hdmi_rockchip_get_property()
2936 if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) in dw_hdmi_rockchip_get_property()
2938 if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) in dw_hdmi_rockchip_get_property()
2940 if (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) in dw_hdmi_rockchip_get_property()
2943 } else if (property == hdmi->outputmode_capacity) { in dw_hdmi_rockchip_get_property()
2953 } else if (property == hdmi->quant_range) { in dw_hdmi_rockchip_get_property()
2954 *val = hdmi->hdmi_quant_range; in dw_hdmi_rockchip_get_property()
2960 } else if (property == hdmi->output_hdmi_dvi) { in dw_hdmi_rockchip_get_property()
2961 *val = hdmi->force_output; in dw_hdmi_rockchip_get_property()
2963 } else if (property == hdmi->output_type_capacity) { in dw_hdmi_rockchip_get_property()
2964 if (!hdmi->is_hdmi_qp) in dw_hdmi_rockchip_get_property()
2965 *val = dw_hdmi_get_output_type_cap(hdmi->hdmi); in dw_hdmi_rockchip_get_property()
2967 *val = dw_hdmi_qp_get_output_type_cap(hdmi->hdmi_qp); in dw_hdmi_rockchip_get_property()
2969 } else if (property == hdmi->allm_capacity) { in dw_hdmi_rockchip_get_property()
2970 *val = !!(hdmi->add_func & SUPPORT_HDMI_ALLM); in dw_hdmi_rockchip_get_property()
2972 } else if (property == hdmi->allm_enable) { in dw_hdmi_rockchip_get_property()
2973 *val = hdmi->enable_allm; in dw_hdmi_rockchip_get_property()
2994 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); in dw_hdmi_rockchip_encoder_mode_set() local
3009 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_encoder_mode_set()
3011 if (hdmi->link_cfg.dsc_mode) in dw_hdmi_rockchip_encoder_mode_set()
3012 dw_hdmi_qp_dsc_configure(hdmi, s, crtc->state); in dw_hdmi_rockchip_encoder_mode_set()
3014 phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); in dw_hdmi_rockchip_encoder_mode_set()
3017 clk_set_rate(hdmi->phyref_clk, adj->crtc_clock * 1000); in dw_hdmi_rockchip_encoder_mode_set()
3030 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_genphy_disable() local
3032 while (hdmi->phy->power_count > 0) in dw_hdmi_rockchip_genphy_disable()
3033 phy_power_off(hdmi->phy); in dw_hdmi_rockchip_genphy_disable()
3041 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rockchip_genphy_init() local
3045 return phy_power_on(hdmi->phy); in dw_hdmi_rockchip_genphy_init()
3050 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3228_setup_hpd() local
3054 regmap_write(hdmi->regmap, in dw_hdmi_rk3228_setup_hpd()
3061 regmap_write(hdmi->regmap, in dw_hdmi_rk3228_setup_hpd()
3070 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3328_read_hpd() local
3076 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_read_hpd()
3081 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_read_hpd()
3090 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3328_setup_hpd() local
3095 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
3100 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
3105 regmap_write(hdmi->regmap, in dw_hdmi_rk3328_setup_hpd()
3115 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_qp_rockchip_phy_disable() local
3117 while (hdmi->phy->power_count > 0) in dw_hdmi_qp_rockchip_phy_disable()
3118 phy_power_off(hdmi->phy); in dw_hdmi_qp_rockchip_phy_disable()
3124 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_qp_rockchip_genphy_init() local
3128 return phy_power_on(hdmi->phy); in dw_hdmi_qp_rockchip_genphy_init()
3136 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3588_read_hpd() local
3138 regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val); in dw_hdmi_rk3588_read_hpd()
3140 if (!hdmi->id) { in dw_hdmi_rk3588_read_hpd()
3142 hdmi->hpd_stat = true; in dw_hdmi_rk3588_read_hpd()
3145 hdmi->hpd_stat = false; in dw_hdmi_rk3588_read_hpd()
3150 hdmi->hpd_stat = true; in dw_hdmi_rk3588_read_hpd()
3153 hdmi->hpd_stat = false; in dw_hdmi_rk3588_read_hpd()
3163 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3588_setup_hpd() local
3166 if (!hdmi->id) { in dw_hdmi_rk3588_setup_hpd()
3176 regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); in dw_hdmi_rk3588_setup_hpd()
3182 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; in dw_hdmi_rk3588_phy_set_mode() local
3184 if (!hdmi->phy) in dw_hdmi_rk3588_phy_set_mode()
3189 hdmi->phy_bus_width |= mode_mask; in dw_hdmi_rk3588_phy_set_mode()
3191 hdmi->phy_bus_width &= ~mode_mask; in dw_hdmi_rk3588_phy_set_mode()
3193 phy_set_bus_width(hdmi->phy, hdmi->phy_bus_width); in dw_hdmi_rk3588_phy_set_mode()
3370 { .compatible = "rockchip,rk3228-dw-hdmi",
3373 { .compatible = "rockchip,rk3288-dw-hdmi",
3376 { .compatible = "rockchip,rk3328-dw-hdmi",
3380 .compatible = "rockchip,rk3368-dw-hdmi",
3383 { .compatible = "rockchip,rk3399-dw-hdmi",
3386 { .compatible = "rockchip,rk3528-dw-hdmi",
3389 { .compatible = "rockchip,rk3568-dw-hdmi",
3392 { .compatible = "rockchip,rk3588-dw-hdmi",
3405 struct rockchip_hdmi *hdmi; in dw_hdmi_rockchip_bind() local
3414 hdmi = platform_get_drvdata(pdev); in dw_hdmi_rockchip_bind()
3415 if (!hdmi) in dw_hdmi_rockchip_bind()
3418 plat_data = hdmi->plat_data; in dw_hdmi_rockchip_bind()
3419 hdmi->drm_dev = drm; in dw_hdmi_rockchip_bind()
3421 plat_data->phy_data = hdmi; in dw_hdmi_rockchip_bind()
3464 secondary = rockchip_hdmi_find_by_id(dev->driver, !hdmi->id); in dw_hdmi_rockchip_bind()
3466 if (hdmi->chip_data->split_mode && secondary) { in dw_hdmi_rockchip_bind()
3469 * hdmi can only attach bridge and init encoder/connector in the in dw_hdmi_rockchip_bind()
3470 * last bind hdmi in split mode, or hdmi->hdmi_qp will not be initialized in dw_hdmi_rockchip_bind()
3472 * mode is on and determine the sequence of hdmi bind. in dw_hdmi_rockchip_bind()
3484 encoder = &hdmi->encoder; in dw_hdmi_rockchip_bind()
3500 hdmi->max_tmdsclk = 594000; in dw_hdmi_rockchip_bind()
3502 hdmi->max_tmdsclk = plat_data->max_tmdsclk; in dw_hdmi_rockchip_bind()
3504 hdmi->is_hdmi_qp = plat_data->is_hdmi_qp; in dw_hdmi_rockchip_bind()
3506 hdmi->unsupported_yuv_input = plat_data->unsupported_yuv_input; in dw_hdmi_rockchip_bind()
3507 hdmi->unsupported_deep_color = plat_data->unsupported_deep_color; in dw_hdmi_rockchip_bind()
3509 ret = rockchip_hdmi_parse_dt(hdmi); in dw_hdmi_rockchip_bind()
3511 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n"); in dw_hdmi_rockchip_bind()
3515 ret = clk_prepare_enable(hdmi->aud_clk); in dw_hdmi_rockchip_bind()
3517 dev_err(hdmi->dev, "Failed to enable HDMI aud_clk: %d\n", ret); in dw_hdmi_rockchip_bind()
3521 ret = clk_prepare_enable(hdmi->hpd_clk); in dw_hdmi_rockchip_bind()
3523 dev_err(hdmi->dev, "Failed to enable HDMI hpd_clk: %d\n", ret); in dw_hdmi_rockchip_bind()
3527 ret = clk_prepare_enable(hdmi->hclk_vo1); in dw_hdmi_rockchip_bind()
3529 dev_err(hdmi->dev, "Failed to enable HDMI hclk_vo1: %d\n", ret); in dw_hdmi_rockchip_bind()
3533 ret = clk_prepare_enable(hdmi->earc_clk); in dw_hdmi_rockchip_bind()
3535 dev_err(hdmi->dev, "Failed to enable HDMI earc_clk: %d\n", ret); in dw_hdmi_rockchip_bind()
3539 ret = clk_prepare_enable(hdmi->hdmitx_ref); in dw_hdmi_rockchip_bind()
3541 dev_err(hdmi->dev, "Failed to enable HDMI hdmitx_ref: %d\n", in dw_hdmi_rockchip_bind()
3546 ret = clk_prepare_enable(hdmi->pclk); in dw_hdmi_rockchip_bind()
3548 dev_err(hdmi->dev, "Failed to enable HDMI pclk: %d\n", ret); in dw_hdmi_rockchip_bind()
3552 if (hdmi->chip_data->ddc_en_reg == RK3568_GRF_VO_CON1) { in dw_hdmi_rockchip_bind()
3553 regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, in dw_hdmi_rockchip_bind()
3560 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_bind()
3561 if (!hdmi->id) { in dw_hdmi_rockchip_bind()
3566 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); in dw_hdmi_rockchip_bind()
3570 regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); in dw_hdmi_rockchip_bind()
3574 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); in dw_hdmi_rockchip_bind()
3580 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); in dw_hdmi_rockchip_bind()
3584 regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); in dw_hdmi_rockchip_bind()
3588 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); in dw_hdmi_rockchip_bind()
3590 init_hpd_work(hdmi); in dw_hdmi_rockchip_bind()
3593 ret = clk_prepare_enable(hdmi->phyref_clk); in dw_hdmi_rockchip_bind()
3595 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n", in dw_hdmi_rockchip_bind()
3600 ret = clk_prepare_enable(hdmi->hclk_vio); in dw_hdmi_rockchip_bind()
3602 dev_err(hdmi->dev, "Failed to enable HDMI hclk_vio: %d\n", in dw_hdmi_rockchip_bind()
3607 ret = clk_prepare_enable(hdmi->hclk_vop); in dw_hdmi_rockchip_bind()
3609 dev_err(hdmi->dev, "Failed to enable HDMI hclk_vop: %d\n", in dw_hdmi_rockchip_bind()
3614 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_bind()
3615 if (!hdmi->id) in dw_hdmi_rockchip_bind()
3619 regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); in dw_hdmi_rockchip_bind()
3621 hdmi->hpd_irq = platform_get_irq(pdev, 4); in dw_hdmi_rockchip_bind()
3622 if (hdmi->hpd_irq < 0) in dw_hdmi_rockchip_bind()
3623 return hdmi->hpd_irq; in dw_hdmi_rockchip_bind()
3625 ret = devm_request_threaded_irq(hdmi->dev, hdmi->hpd_irq, in dw_hdmi_rockchip_bind()
3628 IRQF_SHARED, "dw-hdmi-qp-hpd", in dw_hdmi_rockchip_bind()
3629 hdmi); in dw_hdmi_rockchip_bind()
3634 hdmi->phy = devm_phy_optional_get(dev, "hdmi"); in dw_hdmi_rockchip_bind()
3635 if (IS_ERR(hdmi->phy)) { in dw_hdmi_rockchip_bind()
3636 hdmi->phy = devm_phy_optional_get(dev, "hdmi_phy"); in dw_hdmi_rockchip_bind()
3637 if (IS_ERR(hdmi->phy)) { in dw_hdmi_rockchip_bind()
3638 ret = PTR_ERR(hdmi->phy); in dw_hdmi_rockchip_bind()
3640 DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); in dw_hdmi_rockchip_bind()
3645 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_bind()
3646 hdmi->hdmi_qp = dw_hdmi_qp_bind(pdev, &hdmi->encoder, plat_data); in dw_hdmi_rockchip_bind()
3648 if (IS_ERR(hdmi->hdmi_qp)) { in dw_hdmi_rockchip_bind()
3649 ret = PTR_ERR(hdmi->hdmi_qp); in dw_hdmi_rockchip_bind()
3650 drm_encoder_cleanup(&hdmi->encoder); in dw_hdmi_rockchip_bind()
3654 hdmi->sub_dev.connector = plat_data->connector; in dw_hdmi_rockchip_bind()
3655 hdmi->sub_dev.loader_protect = dw_hdmi_rockchip_encoder_loader_protect; in dw_hdmi_rockchip_bind()
3657 hdmi->sub_dev.of_node = secondary->dev->of_node; in dw_hdmi_rockchip_bind()
3659 hdmi->sub_dev.of_node = hdmi->dev->of_node; in dw_hdmi_rockchip_bind()
3661 rockchip_drm_register_sub_dev(&hdmi->sub_dev); in dw_hdmi_rockchip_bind()
3667 secondary->plat_data->left = hdmi->hdmi_qp; in dw_hdmi_rockchip_bind()
3670 secondary->plat_data->right = hdmi->hdmi_qp; in dw_hdmi_rockchip_bind()
3677 hdmi->hdmi = dw_hdmi_bind(pdev, &hdmi->encoder, plat_data); in dw_hdmi_rockchip_bind()
3683 if (IS_ERR(hdmi->hdmi)) { in dw_hdmi_rockchip_bind()
3684 ret = PTR_ERR(hdmi->hdmi); in dw_hdmi_rockchip_bind()
3685 drm_encoder_cleanup(&hdmi->encoder); in dw_hdmi_rockchip_bind()
3686 clk_disable_unprepare(hdmi->aud_clk); in dw_hdmi_rockchip_bind()
3687 clk_disable_unprepare(hdmi->phyref_clk); in dw_hdmi_rockchip_bind()
3688 clk_disable_unprepare(hdmi->hclk_vop); in dw_hdmi_rockchip_bind()
3689 clk_disable_unprepare(hdmi->hpd_clk); in dw_hdmi_rockchip_bind()
3690 clk_disable_unprepare(hdmi->hclk_vo1); in dw_hdmi_rockchip_bind()
3691 clk_disable_unprepare(hdmi->earc_clk); in dw_hdmi_rockchip_bind()
3692 clk_disable_unprepare(hdmi->hdmitx_ref); in dw_hdmi_rockchip_bind()
3693 clk_disable_unprepare(hdmi->pclk); in dw_hdmi_rockchip_bind()
3697 hdmi->sub_dev.connector = plat_data->connector; in dw_hdmi_rockchip_bind()
3698 hdmi->sub_dev.of_node = dev->of_node; in dw_hdmi_rockchip_bind()
3699 rockchip_drm_register_sub_dev(&hdmi->sub_dev); in dw_hdmi_rockchip_bind()
3708 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); in dw_hdmi_rockchip_unbind() local
3710 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_unbind()
3711 cancel_delayed_work(&hdmi->work); in dw_hdmi_rockchip_unbind()
3712 flush_workqueue(hdmi->workqueue); in dw_hdmi_rockchip_unbind()
3713 destroy_workqueue(hdmi->workqueue); in dw_hdmi_rockchip_unbind()
3716 if (hdmi->sub_dev.connector) in dw_hdmi_rockchip_unbind()
3717 rockchip_drm_unregister_sub_dev(&hdmi->sub_dev); in dw_hdmi_rockchip_unbind()
3719 if (hdmi->is_hdmi_qp) in dw_hdmi_rockchip_unbind()
3720 dw_hdmi_qp_unbind(hdmi->hdmi_qp); in dw_hdmi_rockchip_unbind()
3722 dw_hdmi_unbind(hdmi->hdmi); in dw_hdmi_rockchip_unbind()
3723 clk_disable_unprepare(hdmi->aud_clk); in dw_hdmi_rockchip_unbind()
3724 clk_disable_unprepare(hdmi->phyref_clk); in dw_hdmi_rockchip_unbind()
3725 clk_disable_unprepare(hdmi->hclk_vop); in dw_hdmi_rockchip_unbind()
3726 clk_disable_unprepare(hdmi->hpd_clk); in dw_hdmi_rockchip_unbind()
3727 clk_disable_unprepare(hdmi->hclk_vo1); in dw_hdmi_rockchip_unbind()
3728 clk_disable_unprepare(hdmi->earc_clk); in dw_hdmi_rockchip_unbind()
3729 clk_disable_unprepare(hdmi->hdmitx_ref); in dw_hdmi_rockchip_unbind()
3730 clk_disable_unprepare(hdmi->pclk); in dw_hdmi_rockchip_unbind()
3740 struct rockchip_hdmi *hdmi; in dw_hdmi_rockchip_probe() local
3745 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); in dw_hdmi_rockchip_probe()
3746 if (!hdmi) in dw_hdmi_rockchip_probe()
3749 id = of_alias_get_id(pdev->dev.of_node, "hdmi"); in dw_hdmi_rockchip_probe()
3753 hdmi->id = id; in dw_hdmi_rockchip_probe()
3754 hdmi->dev = &pdev->dev; in dw_hdmi_rockchip_probe()
3762 plat_data->id = hdmi->id; in dw_hdmi_rockchip_probe()
3763 hdmi->plat_data = plat_data; in dw_hdmi_rockchip_probe()
3764 hdmi->chip_data = plat_data->phy_data; in dw_hdmi_rockchip_probe()
3766 platform_set_drvdata(pdev, hdmi); in dw_hdmi_rockchip_probe()
3775 struct rockchip_hdmi *hdmi = dev_get_drvdata(&pdev->dev); in dw_hdmi_rockchip_shutdown() local
3777 if (!hdmi) in dw_hdmi_rockchip_shutdown()
3780 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_shutdown()
3781 if (hdmi->hpd_irq) in dw_hdmi_rockchip_shutdown()
3782 disable_irq(hdmi->hpd_irq); in dw_hdmi_rockchip_shutdown()
3783 cancel_delayed_work(&hdmi->work); in dw_hdmi_rockchip_shutdown()
3784 flush_workqueue(hdmi->workqueue); in dw_hdmi_rockchip_shutdown()
3785 dw_hdmi_qp_suspend(hdmi->dev, hdmi->hdmi_qp); in dw_hdmi_rockchip_shutdown()
3787 if (hdmi->hpd_gpiod) { in dw_hdmi_rockchip_shutdown()
3788 disable_irq(hdmi->hpd_irq); in dw_hdmi_rockchip_shutdown()
3789 if (hdmi->hpd_wake_en) in dw_hdmi_rockchip_shutdown()
3790 disable_irq_wake(hdmi->hpd_irq); in dw_hdmi_rockchip_shutdown()
3792 dw_hdmi_suspend(hdmi->hdmi); in dw_hdmi_rockchip_shutdown()
3807 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); in dw_hdmi_rockchip_suspend() local
3809 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_suspend()
3810 if (hdmi->hpd_irq) in dw_hdmi_rockchip_suspend()
3811 disable_irq(hdmi->hpd_irq); in dw_hdmi_rockchip_suspend()
3812 dw_hdmi_qp_suspend(dev, hdmi->hdmi_qp); in dw_hdmi_rockchip_suspend()
3814 if (hdmi->hpd_gpiod) in dw_hdmi_rockchip_suspend()
3815 disable_irq(hdmi->hpd_irq); in dw_hdmi_rockchip_suspend()
3816 dw_hdmi_suspend(hdmi->hdmi); in dw_hdmi_rockchip_suspend()
3825 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); in dw_hdmi_rockchip_resume() local
3828 if (hdmi->is_hdmi_qp) { in dw_hdmi_rockchip_resume()
3829 if (!hdmi->id) { in dw_hdmi_rockchip_resume()
3834 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); in dw_hdmi_rockchip_resume()
3838 regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); in dw_hdmi_rockchip_resume()
3842 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); in dw_hdmi_rockchip_resume()
3848 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON6, val); in dw_hdmi_rockchip_resume()
3852 regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); in dw_hdmi_rockchip_resume()
3856 regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); in dw_hdmi_rockchip_resume()
3859 dw_hdmi_qp_resume(dev, hdmi->hdmi_qp); in dw_hdmi_rockchip_resume()
3860 if (hdmi->hpd_irq) in dw_hdmi_rockchip_resume()
3861 enable_irq(hdmi->hpd_irq); in dw_hdmi_rockchip_resume()
3862 drm_helper_hpd_irq_event(hdmi->drm_dev); in dw_hdmi_rockchip_resume()
3864 if (hdmi->hpd_gpiod) { in dw_hdmi_rockchip_resume()
3865 dw_hdmi_rk3528_gpio_hpd_init(hdmi); in dw_hdmi_rockchip_resume()
3866 enable_irq(hdmi->hpd_irq); in dw_hdmi_rockchip_resume()
3868 dw_hdmi_resume(hdmi->hdmi); in dw_hdmi_rockchip_resume()