Lines Matching refs:dsi2
300 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, in grf_field_write() argument
303 const u32 field = dsi2->id ? in grf_field_write()
304 dsi2->pdata->dsi1_grf_reg_fields[index] : in grf_field_write()
305 dsi2->pdata->dsi0_grf_reg_fields[index]; in grf_field_write()
316 regmap_write(dsi2->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16)); in grf_field_write()
319 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) in cri_fifos_wait_avail() argument
325 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, sts, in cri_fifos_wait_avail()
329 DRM_DEV_ERROR(dsi2->dev, "command interface is busy\n"); in cri_fifos_wait_avail()
336 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) in dw_mipi_dsi2_irq_enable() argument
339 regmap_write(dsi2->regmap, DSI2_INT_MASK_PHY, 0x1); in dw_mipi_dsi2_irq_enable()
340 regmap_write(dsi2->regmap, DSI2_INT_MASK_TO, 0xf); in dw_mipi_dsi2_irq_enable()
341 regmap_write(dsi2->regmap, DSI2_INT_MASK_ACK, 0x1); in dw_mipi_dsi2_irq_enable()
342 regmap_write(dsi2->regmap, DSI2_INT_MASK_IPI, 0x1); in dw_mipi_dsi2_irq_enable()
343 regmap_write(dsi2->regmap, DSI2_INT_MASK_FIFO, 0x1); in dw_mipi_dsi2_irq_enable()
344 regmap_write(dsi2->regmap, DSI2_INT_MASK_PRI, 0x1); in dw_mipi_dsi2_irq_enable()
345 regmap_write(dsi2->regmap, DSI2_INT_MASK_CRI, 0x1); in dw_mipi_dsi2_irq_enable()
347 regmap_write(dsi2->regmap, DSI2_INT_MASK_PHY, 0x0); in dw_mipi_dsi2_irq_enable()
348 regmap_write(dsi2->regmap, DSI2_INT_MASK_TO, 0x0); in dw_mipi_dsi2_irq_enable()
349 regmap_write(dsi2->regmap, DSI2_INT_MASK_ACK, 0x0); in dw_mipi_dsi2_irq_enable()
350 regmap_write(dsi2->regmap, DSI2_INT_MASK_IPI, 0x0); in dw_mipi_dsi2_irq_enable()
351 regmap_write(dsi2->regmap, DSI2_INT_MASK_FIFO, 0x0); in dw_mipi_dsi2_irq_enable()
352 regmap_write(dsi2->regmap, DSI2_INT_MASK_PRI, 0x0); in dw_mipi_dsi2_irq_enable()
353 regmap_write(dsi2->regmap, DSI2_INT_MASK_CRI, 0x0); in dw_mipi_dsi2_irq_enable()
357 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) in mipi_dcphy_power_on() argument
359 if (dsi2->phy_enabled) in mipi_dcphy_power_on()
362 if (dsi2->dcphy) in mipi_dcphy_power_on()
363 phy_power_on(dsi2->dcphy); in mipi_dcphy_power_on()
365 dsi2->phy_enabled = true; in mipi_dcphy_power_on()
368 static void mipi_dcphy_power_off(struct dw_mipi_dsi2 *dsi2) in mipi_dcphy_power_off() argument
370 if (!dsi2->phy_enabled) in mipi_dcphy_power_off()
373 if (dsi2->dcphy) in mipi_dcphy_power_off()
374 phy_power_off(dsi2->dcphy); in mipi_dcphy_power_off()
376 dsi2->phy_enabled = false; in mipi_dcphy_power_off()
379 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_set_vid_mode() argument
384 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) in dw_mipi_dsi2_set_vid_mode()
387 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) in dw_mipi_dsi2_set_vid_mode()
390 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) in dw_mipi_dsi2_set_vid_mode()
393 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) in dw_mipi_dsi2_set_vid_mode()
395 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in dw_mipi_dsi2_set_vid_mode()
400 regmap_write(dsi2->regmap, DSI2_DSI_VID_TX_CFG, val); in dw_mipi_dsi2_set_vid_mode()
402 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, VIDEO_MODE); in dw_mipi_dsi2_set_vid_mode()
403 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS, in dw_mipi_dsi2_set_vid_mode()
407 dev_err(dsi2->dev, "failed to enter video mode\n"); in dw_mipi_dsi2_set_vid_mode()
410 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_set_data_stream_mode() argument
415 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, DATA_STREAM_MODE); in dw_mipi_dsi2_set_data_stream_mode()
416 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS, in dw_mipi_dsi2_set_data_stream_mode()
420 dev_err(dsi2->dev, "failed to enter data stream mode\n"); in dw_mipi_dsi2_set_data_stream_mode()
423 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_set_cmd_mode() argument
428 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, COMMAND_MODE); in dw_mipi_dsi2_set_cmd_mode()
429 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS, in dw_mipi_dsi2_set_cmd_mode()
433 dev_err(dsi2->dev, "failed to enter data stream mode\n"); in dw_mipi_dsi2_set_cmd_mode()
436 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_disable() argument
438 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, 0); in dw_mipi_dsi2_disable()
439 dw_mipi_dsi2_set_cmd_mode(dsi2); in dw_mipi_dsi2_disable()
441 if (dsi2->slave) in dw_mipi_dsi2_disable()
442 dw_mipi_dsi2_disable(dsi2->slave); in dw_mipi_dsi2_disable()
445 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_post_disable() argument
447 dw_mipi_dsi2_irq_enable(dsi2, 0); in dw_mipi_dsi2_post_disable()
448 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET); in dw_mipi_dsi2_post_disable()
449 mipi_dcphy_power_off(dsi2); in dw_mipi_dsi2_post_disable()
450 pm_runtime_put(dsi2->dev); in dw_mipi_dsi2_post_disable()
452 if (dsi2->slave) in dw_mipi_dsi2_post_disable()
453 dw_mipi_dsi2_post_disable(dsi2->slave); in dw_mipi_dsi2_post_disable()
459 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder); in dw_mipi_dsi2_encoder_atomic_disable() local
463 if (dsi2->panel) in dw_mipi_dsi2_encoder_atomic_disable()
464 drm_panel_disable(dsi2->panel); in dw_mipi_dsi2_encoder_atomic_disable()
466 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) in dw_mipi_dsi2_encoder_atomic_disable()
469 dw_mipi_dsi2_disable(dsi2); in dw_mipi_dsi2_encoder_atomic_disable()
471 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) in dw_mipi_dsi2_encoder_atomic_disable()
474 if (dsi2->panel) in dw_mipi_dsi2_encoder_atomic_disable()
475 drm_panel_unprepare(dsi2->panel); in dw_mipi_dsi2_encoder_atomic_disable()
477 dw_mipi_dsi2_post_disable(dsi2); in dw_mipi_dsi2_encoder_atomic_disable()
482 if (dsi2->slave) in dw_mipi_dsi2_encoder_atomic_disable()
485 s->output_if &= ~(dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0); in dw_mipi_dsi2_encoder_atomic_disable()
488 static void dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_get_lane_rate() argument
490 struct device *dev = dsi2->dev; in dw_mipi_dsi2_get_lane_rate()
491 const struct drm_display_mode *mode = &dsi2->mode; in dw_mipi_dsi2_get_lane_rate()
498 max_lane_rate = (dsi2->c_option) ? in dw_mipi_dsi2_get_lane_rate()
499 dsi2->pdata->cphy_max_symbol_rate_per_lane : in dw_mipi_dsi2_get_lane_rate()
500 dsi2->pdata->dphy_max_bit_rate_per_lane; in dw_mipi_dsi2_get_lane_rate()
502 lanes = (dsi2->slave || dsi2->master) ? dsi2->lanes * 2 : dsi2->lanes; in dw_mipi_dsi2_get_lane_rate()
503 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); in dw_mipi_dsi2_get_lane_rate()
526 if (dsi2->c_option) in dw_mipi_dsi2_get_lane_rate()
534 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { in dw_mipi_dsi2_get_lane_rate()
547 &dsi2->phy_opts.mipi_dphy); in dw_mipi_dsi2_get_lane_rate()
548 if (dsi2->slave) in dw_mipi_dsi2_get_lane_rate()
550 &dsi2->slave->phy_opts.mipi_dphy); in dw_mipi_dsi2_get_lane_rate()
553 static void dw_mipi_dsi2_set_lane_rate(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_set_lane_rate() argument
557 if (dsi2->dcphy) in dw_mipi_dsi2_set_lane_rate()
558 if (!dsi2->c_option) in dw_mipi_dsi2_set_lane_rate()
559 phy_set_mode(dsi2->dcphy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi2_set_lane_rate()
561 phy_configure(dsi2->dcphy, &dsi2->phy_opts); in dw_mipi_dsi2_set_lane_rate()
562 hs_clk_rate = dsi2->phy_opts.mipi_dphy.hs_clk_rate; in dw_mipi_dsi2_set_lane_rate()
563 dsi2->lane_hs_rate = DIV_ROUND_UP(hs_clk_rate, MSEC_PER_SEC); in dw_mipi_dsi2_set_lane_rate()
566 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_host_softrst() argument
568 if (dsi2->apb_rst) { in dw_mipi_dsi2_host_softrst()
569 reset_control_assert(dsi2->apb_rst); in dw_mipi_dsi2_host_softrst()
571 reset_control_deassert(dsi2->apb_rst); in dw_mipi_dsi2_host_softrst()
574 regmap_write(dsi2->regmap, DSI2_SOFT_RESET, 0x0); in dw_mipi_dsi2_host_softrst()
576 regmap_write(dsi2->regmap, DSI2_SOFT_RESET, in dw_mipi_dsi2_host_softrst()
581 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_phy_mode_cfg() argument
586 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); in dw_mipi_dsi2_phy_mode_cfg()
587 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); in dw_mipi_dsi2_phy_mode_cfg()
588 regmap_write(dsi2->regmap, DSI2_PHY_MODE_CFG, val); in dw_mipi_dsi2_phy_mode_cfg()
591 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_phy_clk_mode_cfg() argument
603 sys_clk = clk_get_rate(dsi2->sys_clk) / USEC_PER_SEC; in dw_mipi_dsi2_phy_clk_mode_cfg()
607 regmap_write(dsi2->regmap, DSI2_PHY_CLK_CFG, val); in dw_mipi_dsi2_phy_clk_mode_cfg()
610 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_phy_ratio_cfg() argument
612 struct drm_display_mode *mode = &dsi2->mode; in dw_mipi_dsi2_phy_ratio_cfg()
613 u64 sys_clk = clk_get_rate(dsi2->sys_clk); in dw_mipi_dsi2_phy_ratio_cfg()
622 if (dsi2->c_option) in dw_mipi_dsi2_phy_ratio_cfg()
623 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); in dw_mipi_dsi2_phy_ratio_cfg()
625 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); in dw_mipi_dsi2_phy_ratio_cfg()
632 regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG, in dw_mipi_dsi2_phy_ratio_cfg()
639 regmap_write(dsi2->regmap, DSI2_PHY_SYS_RATIO_MAN_CFG, in dw_mipi_dsi2_phy_ratio_cfg()
643 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg() argument
645 struct phy_configure_opts_mipi_dphy *cfg = &dsi2->phy_opts.mipi_dphy; in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
649 hstx_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
657 regmap_write(dsi2->regmap, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
662 regmap_write(dsi2->regmap, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); in dw_mipi_dsi2_lp2hs_or_hs2lp_cfg()
665 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_phy_init() argument
667 dw_mipi_dsi2_phy_mode_cfg(dsi2); in dw_mipi_dsi2_phy_init()
668 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); in dw_mipi_dsi2_phy_init()
669 dw_mipi_dsi2_phy_ratio_cfg(dsi2); in dw_mipi_dsi2_phy_init()
670 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); in dw_mipi_dsi2_phy_init()
675 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_tx_option_set() argument
681 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) in dw_mipi_dsi2_tx_option_set()
684 regmap_write(dsi2->regmap, DSI2_DSI_GENERAL_CFG, val); in dw_mipi_dsi2_tx_option_set()
685 regmap_write(dsi2->regmap, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); in dw_mipi_dsi2_tx_option_set()
687 if (dsi2->scrambling_en) in dw_mipi_dsi2_tx_option_set()
688 regmap_write(dsi2->regmap, DSI2_DSI_SCRAMBLING_CFG, in dw_mipi_dsi2_tx_option_set()
692 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_ipi_color_coding_cfg() argument
696 switch (dsi2->format) { in dw_mipi_dsi2_ipi_color_coding_cfg()
711 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); in dw_mipi_dsi2_ipi_color_coding_cfg()
712 regmap_write(dsi2->regmap, DSI2_IPI_COLOR_MAN_CFG, val); in dw_mipi_dsi2_ipi_color_coding_cfg()
713 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); in dw_mipi_dsi2_ipi_color_coding_cfg()
715 if (dsi2->dsc_enable) in dw_mipi_dsi2_ipi_color_coding_cfg()
716 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); in dw_mipi_dsi2_ipi_color_coding_cfg()
719 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_ipi_set() argument
721 struct drm_display_mode *mode = &dsi2->mode; in dw_mipi_dsi2_ipi_set()
728 if (dsi2->slave || dsi2->master) in dw_mipi_dsi2_ipi_set()
733 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); in dw_mipi_dsi2_ipi_set()
735 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); in dw_mipi_dsi2_ipi_set()
741 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) in dw_mipi_dsi2_ipi_set()
755 if (dsi2->c_option) in dw_mipi_dsi2_ipi_set()
756 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); in dw_mipi_dsi2_ipi_set()
758 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); in dw_mipi_dsi2_ipi_set()
762 regmap_write(dsi2->regmap, DSI2_IPI_VID_HSA_MAN_CFG, in dw_mipi_dsi2_ipi_set()
767 regmap_write(dsi2->regmap, DSI2_IPI_VID_HBP_MAN_CFG, in dw_mipi_dsi2_ipi_set()
772 regmap_write(dsi2->regmap, DSI2_IPI_VID_HACT_MAN_CFG, in dw_mipi_dsi2_ipi_set()
777 regmap_write(dsi2->regmap, DSI2_IPI_VID_HLINE_MAN_CFG, in dw_mipi_dsi2_ipi_set()
780 regmap_write(dsi2->regmap, DSI2_IPI_VID_VSA_MAN_CFG, in dw_mipi_dsi2_ipi_set()
782 regmap_write(dsi2->regmap, DSI2_IPI_VID_VBP_MAN_CFG, in dw_mipi_dsi2_ipi_set()
784 regmap_write(dsi2->regmap, DSI2_IPI_VID_VACT_MAN_CFG, in dw_mipi_dsi2_ipi_set()
786 regmap_write(dsi2->regmap, DSI2_IPI_VID_VFP_MAN_CFG, in dw_mipi_dsi2_ipi_set()
791 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) in dw_mipi_dsi2_work_mode() argument
798 regmap_write(dsi2->regmap, MANUAL_MODE_CFG, mode); in dw_mipi_dsi2_work_mode()
801 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_pre_enable() argument
803 pm_runtime_get_sync(dsi2->dev); in dw_mipi_dsi2_pre_enable()
805 dw_mipi_dsi2_host_softrst(dsi2); in dw_mipi_dsi2_pre_enable()
806 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET); in dw_mipi_dsi2_pre_enable()
810 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); in dw_mipi_dsi2_pre_enable()
811 dw_mipi_dsi2_phy_init(dsi2); in dw_mipi_dsi2_pre_enable()
812 dw_mipi_dsi2_tx_option_set(dsi2); in dw_mipi_dsi2_pre_enable()
813 dw_mipi_dsi2_irq_enable(dsi2, 1); in dw_mipi_dsi2_pre_enable()
814 mipi_dcphy_power_on(dsi2); in dw_mipi_dsi2_pre_enable()
820 if (!(dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) in dw_mipi_dsi2_pre_enable()
821 regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG, in dw_mipi_dsi2_pre_enable()
824 regmap_write(dsi2->regmap, DSI2_PWR_UP, POWER_UP); in dw_mipi_dsi2_pre_enable()
825 dw_mipi_dsi2_set_cmd_mode(dsi2); in dw_mipi_dsi2_pre_enable()
827 if (dsi2->slave) in dw_mipi_dsi2_pre_enable()
828 dw_mipi_dsi2_pre_enable(dsi2->slave); in dw_mipi_dsi2_pre_enable()
831 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_enable() argument
833 dw_mipi_dsi2_ipi_set(dsi2); in dw_mipi_dsi2_enable()
835 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) in dw_mipi_dsi2_enable()
836 dw_mipi_dsi2_set_vid_mode(dsi2); in dw_mipi_dsi2_enable()
838 dw_mipi_dsi2_set_data_stream_mode(dsi2); in dw_mipi_dsi2_enable()
840 if (dsi2->slave) in dw_mipi_dsi2_enable()
841 dw_mipi_dsi2_enable(dsi2->slave); in dw_mipi_dsi2_enable()
844 static int dw_mipi_dsi2_encoder_mode_set(struct dw_mipi_dsi2 *dsi2, in dw_mipi_dsi2_encoder_mode_set() argument
847 struct drm_encoder *encoder = &dsi2->encoder; in dw_mipi_dsi2_encoder_mode_set()
852 struct drm_display_mode *mode = &dsi2->mode; in dw_mipi_dsi2_encoder_mode_set()
864 dev_err(dsi2->dev, "failed to get crtc state\n"); in dw_mipi_dsi2_encoder_mode_set()
871 if (dsi2->dual_connector_split) in dw_mipi_dsi2_encoder_mode_set()
874 if (dsi2->slave) in dw_mipi_dsi2_encoder_mode_set()
875 drm_mode_copy(&dsi2->slave->mode, mode); in dw_mipi_dsi2_encoder_mode_set()
883 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder); in dw_mipi_dsi2_encoder_atomic_enable() local
886 ret = dw_mipi_dsi2_encoder_mode_set(dsi2, state); in dw_mipi_dsi2_encoder_atomic_enable()
888 dev_err(dsi2->dev, "failed to set dsi2 mode\n"); in dw_mipi_dsi2_encoder_atomic_enable()
892 dw_mipi_dsi2_get_lane_rate(dsi2); in dw_mipi_dsi2_encoder_atomic_enable()
894 if (dsi2->dcphy) in dw_mipi_dsi2_encoder_atomic_enable()
895 dw_mipi_dsi2_set_lane_rate(dsi2); in dw_mipi_dsi2_encoder_atomic_enable()
897 if (dsi2->slave && dsi2->slave->dcphy) in dw_mipi_dsi2_encoder_atomic_enable()
898 dw_mipi_dsi2_set_lane_rate(dsi2->slave); in dw_mipi_dsi2_encoder_atomic_enable()
900 dw_mipi_dsi2_pre_enable(dsi2); in dw_mipi_dsi2_encoder_atomic_enable()
902 if (dsi2->panel) in dw_mipi_dsi2_encoder_atomic_enable()
903 drm_panel_prepare(dsi2->panel); in dw_mipi_dsi2_encoder_atomic_enable()
905 dw_mipi_dsi2_enable(dsi2); in dw_mipi_dsi2_encoder_atomic_enable()
907 if (dsi2->panel) in dw_mipi_dsi2_encoder_atomic_enable()
908 drm_panel_enable(dsi2->panel); in dw_mipi_dsi2_encoder_atomic_enable()
910 DRM_DEV_INFO(dsi2->dev, "final DSI-Link bandwidth: %u x %d %s\n", in dw_mipi_dsi2_encoder_atomic_enable()
911 dsi2->lane_hs_rate, in dw_mipi_dsi2_encoder_atomic_enable()
912 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes, in dw_mipi_dsi2_encoder_atomic_enable()
913 dsi2->c_option ? "Ksps" : "Kbps"); in dw_mipi_dsi2_encoder_atomic_enable()
923 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder); in dw_mipi_dsi2_encoder_atomic_check() local
927 switch (dsi2->format) { in dw_mipi_dsi2_encoder_atomic_check()
948 s->output_if |= dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; in dw_mipi_dsi2_encoder_atomic_check()
954 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { in dw_mipi_dsi2_encoder_atomic_check()
956 s->soft_te = dsi2->te_gpio ? true : false; in dw_mipi_dsi2_encoder_atomic_check()
960 if (dsi2->slave) { in dw_mipi_dsi2_encoder_atomic_check()
962 if (dsi2->data_swap) in dw_mipi_dsi2_encoder_atomic_check()
968 if (dsi2->dual_connector_split) { in dw_mipi_dsi2_encoder_atomic_check()
971 if (dsi2->left_display) in dw_mipi_dsi2_encoder_atomic_check()
972 s->output_if_left_panel |= dsi2->id ? in dw_mipi_dsi2_encoder_atomic_check()
977 if (dsi2->dsc_enable) { in dw_mipi_dsi2_encoder_atomic_check()
979 s->dsc_sink_cap.version_major = dsi2->version_major; in dw_mipi_dsi2_encoder_atomic_check()
980 s->dsc_sink_cap.version_minor = dsi2->version_minor; in dw_mipi_dsi2_encoder_atomic_check()
981 s->dsc_sink_cap.slice_width = dsi2->slice_width; in dw_mipi_dsi2_encoder_atomic_check()
982 s->dsc_sink_cap.slice_height = dsi2->slice_height; in dw_mipi_dsi2_encoder_atomic_check()
987 memcpy(&s->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); in dw_mipi_dsi2_encoder_atomic_check()
993 static void dw_mipi_dsi2_loader_protect(struct dw_mipi_dsi2 *dsi2, bool on) in dw_mipi_dsi2_loader_protect() argument
996 pm_runtime_get_sync(dsi2->dev); in dw_mipi_dsi2_loader_protect()
997 phy_init(dsi2->dcphy); in dw_mipi_dsi2_loader_protect()
998 dsi2->phy_enabled = true; in dw_mipi_dsi2_loader_protect()
999 if (dsi2->dcphy) in dw_mipi_dsi2_loader_protect()
1000 dsi2->dcphy->power_count++; in dw_mipi_dsi2_loader_protect()
1002 pm_runtime_put(dsi2->dev); in dw_mipi_dsi2_loader_protect()
1003 phy_exit(dsi2->dcphy); in dw_mipi_dsi2_loader_protect()
1004 dsi2->phy_enabled = false; in dw_mipi_dsi2_loader_protect()
1005 if (dsi2->dcphy) in dw_mipi_dsi2_loader_protect()
1006 dsi2->dcphy->power_count--; in dw_mipi_dsi2_loader_protect()
1009 if (dsi2->slave) in dw_mipi_dsi2_loader_protect()
1010 dw_mipi_dsi2_loader_protect(dsi2->slave, on); in dw_mipi_dsi2_loader_protect()
1016 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder); in dw_mipi_dsi2_encoder_loader_protect() local
1018 if (dsi2->panel) in dw_mipi_dsi2_encoder_loader_protect()
1019 panel_simple_loader_protect(dsi2->panel); in dw_mipi_dsi2_encoder_loader_protect()
1021 dw_mipi_dsi2_loader_protect(dsi2, on); in dw_mipi_dsi2_encoder_loader_protect()
1035 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector); in dw_mipi_dsi2_connector_get_modes() local
1037 if (dsi2->bridge && (dsi2->bridge->ops & DRM_BRIDGE_OP_MODES)) in dw_mipi_dsi2_connector_get_modes()
1038 return drm_bridge_get_modes(dsi2->bridge, connector); in dw_mipi_dsi2_connector_get_modes()
1040 if (dsi2->panel) in dw_mipi_dsi2_connector_get_modes()
1041 return drm_panel_get_modes(dsi2->panel, connector); in dw_mipi_dsi2_connector_get_modes()
1050 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector); in dw_mipi_dsi2_connector_mode_valid() local
1052 u8 min_pixels = dsi2->slave ? 8 : 4; in dw_mipi_dsi2_connector_mode_valid()
1098 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector); in dw_mipi_dsi2_connector_detect() local
1100 if (dsi2->bridge && (dsi2->bridge->ops & DRM_BRIDGE_OP_DETECT)) in dw_mipi_dsi2_connector_detect()
1101 return drm_bridge_detect(dsi2->bridge); in dw_mipi_dsi2_connector_detect()
1119 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector); in dw_mipi_dsi2_atomic_connector_get_property() local
1122 switch (dsi2->split_area) { in dw_mipi_dsi2_atomic_connector_get_property()
1148 static int dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_dual_channel_probe() argument
1153 np = of_parse_phandle(dsi2->dev->of_node, "rockchip,dual-channel", 0); in dw_mipi_dsi2_dual_channel_probe()
1155 dsi2->data_swap = of_property_read_bool(dsi2->dev->of_node, in dw_mipi_dsi2_dual_channel_probe()
1158 dsi2->slave = platform_get_drvdata(secondary); in dw_mipi_dsi2_dual_channel_probe()
1161 if (!dsi2->slave) in dw_mipi_dsi2_dual_channel_probe()
1164 dsi2->slave->master = dsi2; in dw_mipi_dsi2_dual_channel_probe()
1165 dsi2->lanes /= 2; in dw_mipi_dsi2_dual_channel_probe()
1167 dsi2->slave->lanes = dsi2->lanes; in dw_mipi_dsi2_dual_channel_probe()
1168 dsi2->slave->channel = dsi2->channel; in dw_mipi_dsi2_dual_channel_probe()
1169 dsi2->slave->format = dsi2->format; in dw_mipi_dsi2_dual_channel_probe()
1170 dsi2->slave->mode_flags = dsi2->mode_flags; in dw_mipi_dsi2_dual_channel_probe()
1178 struct dw_mipi_dsi2 *dsi2 = (struct dw_mipi_dsi2 *)dev_id; in dw_mipi_dsi2_te_irq_handler() local
1179 struct drm_encoder *encoder = &dsi2->encoder; in dw_mipi_dsi2_te_irq_handler()
1187 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2, in dw_mipi_dsi2_get_dsc_params_from_sink() argument
1207 dsi2->c_option = of_property_read_bool(np, "phy-c-option"); in dw_mipi_dsi2_get_dsc_params_from_sink()
1208 dsi2->scrambling_en = of_property_read_bool(np, "scrambling-enable"); in dw_mipi_dsi2_get_dsc_params_from_sink()
1209 dsi2->dsc_enable = of_property_read_bool(np, "compressed-data"); in dw_mipi_dsi2_get_dsc_params_from_sink()
1211 if (dsi2->slave) { in dw_mipi_dsi2_get_dsc_params_from_sink()
1212 dsi2->slave->c_option = dsi2->c_option; in dw_mipi_dsi2_get_dsc_params_from_sink()
1213 dsi2->slave->scrambling_en = dsi2->scrambling_en; in dw_mipi_dsi2_get_dsc_params_from_sink()
1214 dsi2->slave->dsc_enable = dsi2->dsc_enable; in dw_mipi_dsi2_get_dsc_params_from_sink()
1217 of_property_read_u32(np, "slice-width", &dsi2->slice_width); in dw_mipi_dsi2_get_dsc_params_from_sink()
1218 of_property_read_u32(np, "slice-height", &dsi2->slice_height); in dw_mipi_dsi2_get_dsc_params_from_sink()
1219 of_property_read_u8(np, "version-major", &dsi2->version_major); in dw_mipi_dsi2_get_dsc_params_from_sink()
1220 of_property_read_u8(np, "version-minor", &dsi2->version_minor); in dw_mipi_dsi2_get_dsc_params_from_sink()
1226 d = devm_kmemdup(dsi2->dev, data, len, GFP_KERNEL); in dw_mipi_dsi2_get_dsc_params_from_sink()
1239 dsc_packed_pps = devm_kmemdup(dsi2->dev, d, in dw_mipi_dsi2_get_dsc_params_from_sink()
1252 dsi2->pps = pps; in dw_mipi_dsi2_get_dsc_params_from_sink()
1257 static int dw_mipi_dsi2_connector_init(struct dw_mipi_dsi2 *dsi2) in dw_mipi_dsi2_connector_init() argument
1259 struct drm_encoder *encoder = &dsi2->encoder; in dw_mipi_dsi2_connector_init()
1260 struct drm_connector *connector = &dsi2->connector; in dw_mipi_dsi2_connector_init()
1261 struct drm_device *drm_dev = dsi2->drm_dev; in dw_mipi_dsi2_connector_init()
1262 struct device *dev = dsi2->dev; in dw_mipi_dsi2_connector_init()
1289 static int dw_mipi_dsi2_register_sub_dev(struct dw_mipi_dsi2 *dsi2, in dw_mipi_dsi2_register_sub_dev() argument
1293 struct device *dev = dsi2->dev; in dw_mipi_dsi2_register_sub_dev()
1297 if (dsi2->split_area) in dw_mipi_dsi2_register_sub_dev()
1300 dsi2->split_area); in dw_mipi_dsi2_register_sub_dev()
1302 dsi2->sub_dev.connector = connector; in dw_mipi_dsi2_register_sub_dev()
1303 dsi2->sub_dev.of_node = dev->of_node; in dw_mipi_dsi2_register_sub_dev()
1304 dsi2->sub_dev.loader_protect = dw_mipi_dsi2_encoder_loader_protect; in dw_mipi_dsi2_register_sub_dev()
1305 rockchip_drm_register_sub_dev(&dsi2->sub_dev); in dw_mipi_dsi2_register_sub_dev()
1313 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev); in dw_mipi_dsi2_bind() local
1315 struct drm_encoder *encoder = &dsi2->encoder; in dw_mipi_dsi2_bind()
1316 struct device_node *of_node = dsi2->dev->of_node; in dw_mipi_dsi2_bind()
1321 dsi2->drm_dev = drm_dev; in dw_mipi_dsi2_bind()
1322 ret = dw_mipi_dsi2_dual_channel_probe(dsi2); in dw_mipi_dsi2_bind()
1326 if (dsi2->master) in dw_mipi_dsi2_bind()
1330 &dsi2->panel, &dsi2->bridge); in dw_mipi_dsi2_bind()
1336 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2, dsi2->panel, dsi2->bridge); in dw_mipi_dsi2_bind()
1348 if (dsi2->bridge) { in dw_mipi_dsi2_bind()
1352 dsi2->bridge->driver_private = &dsi2->host; in dw_mipi_dsi2_bind()
1353 dsi2->bridge->encoder = encoder; in dw_mipi_dsi2_bind()
1355 flags = dsi2->bridge->ops & DRM_BRIDGE_OP_MODES ? in dw_mipi_dsi2_bind()
1357 ret = drm_bridge_attach(encoder, dsi2->bridge, NULL, flags); in dw_mipi_dsi2_bind()
1371 if (dsi2->panel || (dsi2->bridge && (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))) { in dw_mipi_dsi2_bind()
1372 ret = dw_mipi_dsi2_connector_init(dsi2); in dw_mipi_dsi2_bind()
1376 connector = &dsi2->connector; in dw_mipi_dsi2_bind()
1380 ret = dw_mipi_dsi2_register_sub_dev(dsi2, connector); in dw_mipi_dsi2_bind()
1385 pm_runtime_enable(dsi2->dev); in dw_mipi_dsi2_bind()
1386 if (dsi2->slave) in dw_mipi_dsi2_bind()
1387 pm_runtime_enable(dsi2->slave->dev); in dw_mipi_dsi2_bind()
1400 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev); in dw_mipi_dsi2_unbind() local
1402 if (dsi2->sub_dev.connector) { in dw_mipi_dsi2_unbind()
1403 rockchip_drm_unregister_sub_dev(&dsi2->sub_dev); in dw_mipi_dsi2_unbind()
1405 if (dsi2->connector.funcs) in dw_mipi_dsi2_unbind()
1406 dsi2->connector.funcs->destroy(&dsi2->connector); in dw_mipi_dsi2_unbind()
1409 pm_runtime_disable(dsi2->dev); in dw_mipi_dsi2_unbind()
1410 if (dsi2->slave) in dw_mipi_dsi2_unbind()
1411 pm_runtime_disable(dsi2->slave->dev); in dw_mipi_dsi2_unbind()
1413 dsi2->encoder.funcs->destroy(&dsi2->encoder); in dw_mipi_dsi2_unbind()
1439 struct dw_mipi_dsi2 *dsi2 = dev_id; in dw_mipi_dsi2_irq_handler() local
1443 regmap_read(dsi2->regmap, INT_ST_MAIN, &int_st); in dw_mipi_dsi2_irq_handler()
1447 DRM_DEV_DEBUG(dsi2->dev, "%s\n", in dw_mipi_dsi2_irq_handler()
1465 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host); in dw_mipi_dsi2_host_attach() local
1467 if (dsi2->master) in dw_mipi_dsi2_host_attach()
1473 dsi2->client = device->dev.of_node; in dw_mipi_dsi2_host_attach()
1474 dsi2->lanes = device->lanes; in dw_mipi_dsi2_host_attach()
1475 dsi2->channel = device->channel; in dw_mipi_dsi2_host_attach()
1476 dsi2->format = device->format; in dw_mipi_dsi2_host_attach()
1477 dsi2->mode_flags = device->mode_flags; in dw_mipi_dsi2_host_attach()
1488 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, in dw_mipi_dsi2_read_from_fifo() argument
1495 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode); in dw_mipi_dsi2_read_from_fifo()
1498 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, in dw_mipi_dsi2_read_from_fifo()
1502 DRM_DEV_ERROR(dsi2->dev, "CRI has no available read data\n"); in dw_mipi_dsi2_read_from_fifo()
1506 regmap_read(dsi2->regmap, DSI2_CRI_RX_HDR, &val); in dw_mipi_dsi2_read_from_fifo()
1519 regmap_read(dsi2->regmap, DSI2_CRI_RX_PLD, &val); in dw_mipi_dsi2_read_from_fifo()
1527 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, in dw_mipi_dsi2_transfer() argument
1535 regmap_update_bits(dsi2->regmap, DSI2_DSI_VID_TX_CFG, in dw_mipi_dsi2_transfer()
1543 DRM_DEV_ERROR(dsi2->dev, "failed to create packet: %d\n", ret); in dw_mipi_dsi2_transfer()
1547 ret = cri_fifos_wait_avail(dsi2); in dw_mipi_dsi2_transfer()
1558 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, val); in dw_mipi_dsi2_transfer()
1562 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, val); in dw_mipi_dsi2_transfer()
1572 regmap_write(dsi2->regmap, DSI2_CRI_TX_HDR, mode | val); in dw_mipi_dsi2_transfer()
1574 ret = cri_fifos_wait_avail(dsi2); in dw_mipi_dsi2_transfer()
1579 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); in dw_mipi_dsi2_transfer()
1584 if (dsi2->slave) in dw_mipi_dsi2_transfer()
1585 dw_mipi_dsi2_transfer(dsi2->slave, msg); in dw_mipi_dsi2_transfer()
1593 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host); in dw_mipi_dsi2_host_transfer() local
1595 return dw_mipi_dsi2_transfer(dsi2, msg); in dw_mipi_dsi2_host_transfer()
1607 struct dw_mipi_dsi2 *dsi2; in dw_mipi_dsi2_probe() local
1613 dsi2 = devm_kzalloc(dev, sizeof(*dsi2), GFP_KERNEL); in dw_mipi_dsi2_probe()
1614 if (!dsi2) in dw_mipi_dsi2_probe()
1621 dsi2->dev = dev; in dw_mipi_dsi2_probe()
1622 dsi2->id = id; in dw_mipi_dsi2_probe()
1623 dsi2->pdata = of_device_get_match_data(dev); in dw_mipi_dsi2_probe()
1624 platform_set_drvdata(pdev, dsi2); in dw_mipi_dsi2_probe()
1627 dsi2->dual_connector_split = true; in dw_mipi_dsi2_probe()
1630 dsi2->left_display = true; in dw_mipi_dsi2_probe()
1633 if (device_property_read_u32(dev, "split-area", &dsi2->split_area)) in dw_mipi_dsi2_probe()
1634 dsi2->split_area = 0; in dw_mipi_dsi2_probe()
1641 dsi2->irq = platform_get_irq(pdev, 0); in dw_mipi_dsi2_probe()
1642 if (dsi2->irq < 0) in dw_mipi_dsi2_probe()
1643 return dsi2->irq; in dw_mipi_dsi2_probe()
1645 dsi2->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi2_probe()
1646 if (IS_ERR(dsi2->pclk)) { in dw_mipi_dsi2_probe()
1647 ret = PTR_ERR(dsi2->pclk); in dw_mipi_dsi2_probe()
1652 dsi2->sys_clk = devm_clk_get(dev, "sys_clk"); in dw_mipi_dsi2_probe()
1653 if (IS_ERR(dsi2->sys_clk)) { in dw_mipi_dsi2_probe()
1654 ret = PTR_ERR(dsi2->sys_clk); in dw_mipi_dsi2_probe()
1659 dsi2->regmap = devm_regmap_init_mmio(dev, regs, in dw_mipi_dsi2_probe()
1661 if (IS_ERR(dsi2->regmap)) { in dw_mipi_dsi2_probe()
1662 ret = PTR_ERR(dsi2->regmap); in dw_mipi_dsi2_probe()
1667 dsi2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, in dw_mipi_dsi2_probe()
1669 if (IS_ERR(dsi2->grf)) { in dw_mipi_dsi2_probe()
1670 ret = PTR_ERR(dsi2->grf); in dw_mipi_dsi2_probe()
1671 DRM_DEV_ERROR(dsi2->dev, "Unable to get grf: %d\n", ret); in dw_mipi_dsi2_probe()
1675 dsi2->apb_rst = devm_reset_control_get(dev, "apb"); in dw_mipi_dsi2_probe()
1676 if (IS_ERR(dsi2->apb_rst)) { in dw_mipi_dsi2_probe()
1677 ret = PTR_ERR(dsi2->apb_rst); in dw_mipi_dsi2_probe()
1683 dsi2->dcphy = devm_phy_optional_get(dev, "dcphy"); in dw_mipi_dsi2_probe()
1684 if (IS_ERR(dsi2->dcphy)) { in dw_mipi_dsi2_probe()
1685 ret = PTR_ERR(dsi2->dcphy); in dw_mipi_dsi2_probe()
1690 dsi2->te_gpio = devm_gpiod_get_optional(dsi2->dev, "te", GPIOD_IN); in dw_mipi_dsi2_probe()
1691 if (IS_ERR(dsi2->te_gpio)) in dw_mipi_dsi2_probe()
1692 dsi2->te_gpio = NULL; in dw_mipi_dsi2_probe()
1694 if (dsi2->te_gpio) { in dw_mipi_dsi2_probe()
1695 ret = devm_request_threaded_irq(dsi2->dev, gpiod_to_irq(dsi2->te_gpio), in dw_mipi_dsi2_probe()
1698 "PANEL-TE", dsi2); in dw_mipi_dsi2_probe()
1700 dev_err(dsi2->dev, "failed to request TE IRQ: %d\n", ret); in dw_mipi_dsi2_probe()
1705 ret = devm_request_irq(dev, dsi2->irq, dw_mipi_dsi2_irq_handler, in dw_mipi_dsi2_probe()
1706 IRQF_SHARED, dev_name(dev), dsi2); in dw_mipi_dsi2_probe()
1712 dsi2->host.ops = &dw_mipi_dsi2_host_ops; in dw_mipi_dsi2_probe()
1713 dsi2->host.dev = dev; in dw_mipi_dsi2_probe()
1714 ret = mipi_dsi_host_register(&dsi2->host); in dw_mipi_dsi2_probe()
1730 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev); in dw_mipi_dsi2_runtime_suspend() local
1732 clk_disable_unprepare(dsi2->pclk); in dw_mipi_dsi2_runtime_suspend()
1733 clk_disable_unprepare(dsi2->sys_clk); in dw_mipi_dsi2_runtime_suspend()
1740 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev); in dw_mipi_dsi2_runtime_resume() local
1742 clk_prepare_enable(dsi2->pclk); in dw_mipi_dsi2_runtime_resume()
1743 clk_prepare_enable(dsi2->sys_clk); in dw_mipi_dsi2_runtime_resume()