Lines Matching refs:SCRAMBLE_DIS
58 #define SCRAMBLE_DIS BIT(0) macro
1644 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, in dw_dp_link_train_set_pattern()
1645 FIELD_PREP(SCRAMBLE_DIS, 1)); in dw_dp_link_train_set_pattern()
1647 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, in dw_dp_link_train_set_pattern()
1648 FIELD_PREP(SCRAMBLE_DIS, 0)); in dw_dp_link_train_set_pattern()
3457 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, in dw_dp_phy_pattern_update()
3458 FIELD_PREP(SCRAMBLE_DIS, 1)); in dw_dp_phy_pattern_update()
3463 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, in dw_dp_phy_pattern_update()
3464 FIELD_PREP(SCRAMBLE_DIS, 1)); in dw_dp_phy_pattern_update()
3468 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, in dw_dp_phy_pattern_update()
3469 FIELD_PREP(SCRAMBLE_DIS, 0)); in dw_dp_phy_pattern_update()
3475 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, in dw_dp_phy_pattern_update()
3476 FIELD_PREP(SCRAMBLE_DIS, 1)); in dw_dp_phy_pattern_update()
3481 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, in dw_dp_phy_pattern_update()
3482 FIELD_PREP(SCRAMBLE_DIS, 1)); in dw_dp_phy_pattern_update()
3490 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, in dw_dp_phy_pattern_update()
3491 FIELD_PREP(SCRAMBLE_DIS, 0)); in dw_dp_phy_pattern_update()
3496 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, in dw_dp_phy_pattern_update()
3497 FIELD_PREP(SCRAMBLE_DIS, 0)); in dw_dp_phy_pattern_update()