4617 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_ulv_state()  local
4621 	ret = si_convert_power_level_to_smc(rdev, &ulv->pl,  in si_populate_ulv_state()
4630 		if (ulv->one_pcie_lane_in_ulv)  in si_populate_ulv_state()
4646 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_program_ulv_memory_timing_parameters()  local
4650 	ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,  in si_program_ulv_memory_timing_parameters()
4656 				   ulv->volt_change_delay);  in si_program_ulv_memory_timing_parameters()
4681 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_init_smc_table()  local
4741 	if (ulv->supported && ulv->pl.vddc) {  in si_init_smc_table()
4750 		WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);  in si_init_smc_table()
4751 		WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);  in si_init_smc_table()
5120 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_disable_ulv()  local
5122 	if (ulv->supported)  in si_disable_ulv()
5133 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_is_state_ulv_compatible()  local
5137 	if (state->performance_levels[0].mclk != ulv->pl.mclk)  in si_is_state_ulv_compatible()
5145 			if (ulv->pl.vddc <  in si_is_state_ulv_compatible()
5161 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_set_power_state_conditionally_enable_ulv()  local
5163 	if (ulv->supported) {  in si_set_power_state_conditionally_enable_ulv()
5279 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_upload_ulv_state()  local
5282 	if (ulv->supported && ulv->pl.vddc) {  in si_upload_ulv_state()
5638 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_mc_reg_table()  local
5655 	if (ulv->supported && ulv->pl.vddc != 0)  in si_populate_mc_reg_table()
5656 		si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,  in si_populate_mc_reg_table()
6756 		si_pi->ulv.supported = false;  in si_parse_pplib_clock_info()
6757 		si_pi->ulv.pl = *pl;  in si_parse_pplib_clock_info()
6758 		si_pi->ulv.one_pcie_lane_in_ulv = false;  in si_parse_pplib_clock_info()
6759 		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;  in si_parse_pplib_clock_info()
6760 		si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;  in si_parse_pplib_clock_info()
6761 		si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;  in si_parse_pplib_clock_info()